General Description
This device contains six independent gates each of which performs a buffer function.
The open-collector outputs require external pull-up resistors for proper logical operation.

DM7407M
DM7407N  

DM7407-Hex Buffers with High Voltage Open-Collector Outputs

GENERAL DESCRIPTION
The XR-2211 is a monolithic phase-locked loop (PLL) system especially designed for data communications applications.
It is particularly suited for FSK modem applications.
It operates over a wide supply voltage range of 4.5 to 20V and a wide frequency range of 0.01Hz to 300kHz.
It can accommodate analog signals between 10mV and 3V, and can interface with conventional DTL, TTL, and ECL logic families.
The circuit consists of a basic PLL for tracking an input signal within the pass band, a
quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation.
External components are used to independently set center frequency, bandwidth, and output
delay.
An internal voltage reference proportional to the power supply is provided at an output pin.
The XR-2211 is available in 14 pin packages specified for military and industrial temperature ranges.

FEATURES
*Wide Frequency Range, 0.01Hz to 300kHz
*Wide Supply Voltage Range, 4.5V to 20V
*HCMOS/TTL/Logic Compatibility
*FSK Demodulation, with Carrier Detection
*Wide Dynamic Range, 10mV to 3V rms
*Adjustable Tracking Range, +1% to 80%
*Excellent Temp. Stability, +50ppm/°C, max.

APPLICATIONS
*Caller Identification Delivery
*FSK Demodulation
*Data Synchronization
*Tone Decoding
*FM Detection
*Carrier Detection

XR-2211M
XR-2211N
XR-2211P
XR-2211ID

 

XR-2211-FSK Demodulator/Tone Decoder

Descriptions
PT331C is a high speed and high sensitive silicon NPN epitaxial planar phototransistor in a standard 5Φ package.
Due to is water clear epoxy the device is sensitive to visible and near infrared radiation.

Features
*Fast response time
*High photo sensitivity
*Pb free

Applications
*Infrared applied system
*Floppy disk drive
*Optoelectronic switch

 

PT331C-5mm Phototransistor T-1 3/4

DESCRIPTION
The MA31755 is a 16 bit Error Detection and Correction Unit intended for use in high integrity systems for monitoring and correcting data values retrieved from memory.
The EDAC placed in the data bus between the processor and the memory to be protected.
Extra check bits added at each memory location are programmed transparently by the EDAC
during a processor write cycle.
The entire checkword and data combination is verified on read cycles.
If any one bit in the incoming data stream is at fault the EDAC can correct the fault transparently, presenting the corrected 16-bit value to the processor.
An error in two bits can be detected but cannot be corrected.
 Both the correctable and uncorrectable error conditions are signalled to the system to allow the processor to take action as required.
Parity is passed through the device unchanged as data bus bit 16.
Tri-statable bus transceivers with a high drive capability are incorporated at the MD and CB busses which allows the usual bus driver devices to be removed and reduces the overall timing overhead imposed on the data bus.
Although designed primarily for MA31750 application, this part may be used in almost any 16-bit processor system requiring high data integrity.

FEATURES
*Fast Feedthrough (35ns Detect and Correct Cycle)
*16-Bit Operatio*with 6 Check Bits
*Radiatio*Hard CMOS/SOS Technology
*Feedthrough Operation
*Error Corrected/Uncorrected Flags
*High Drive Capability o*Memory Busses

 

MA31755-16-Bit Feedthrough Error Detection & Correction Unit (EDAC)

FUNCTIONAL DESCRIPTION
The DDU39F-series device is a mechanically variable, FAST-TTL interfaced delay line.
The signal input (IN) is reproduced at the tap output (OUT), shifted by an amount which can be adjusted between 7ns and 25ns.
The device operates from a single 5V supply and is TTL interfaced, capable of driving up to 10 TTL loads.

FEATURES
*Ideal for “Set and Forget” applications
*Multi-turn adjustment screw (approx. 15 turns)
*Fits standard 16-pin DIP socket
*Input & output fully TTL interfaced & buffered (10 T2L fan-out capability)
*Resolution: 0.5ns typical
*Adjustment range: 7ns to 25ns
*Output rise time: 4ns typical
*Min. input pulse width: 10ns
*Power dissipation: 230mW maximum
*Operating temperature: 0° to 70°C (Commercial) -55° to 125°C (Military)

APPLICATION NOTES
*HIGH FREQUENCY RESPONSE
The DDU39F tolerances are guaranteed for input pulse widths and periods greater than those
specified in the test conditions.
Although the device will function properly for pulse widths as small as 10ns and periods as small 20ns (for a symmetric input), the delays may deviate from their values at low frequency.
However, for a given input condition, the deviation will be repeatable from pulse to pulse.
Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.
*POWER SUPPLY BYPASSING
The DDU39F relies on a stable power supply to produce repeatable delays within the stated
tolerances.
A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended.
A wide VCC trace and a clean ground plane should be used.

DDU39F
DDU39FM  

DDU39F-MECHANICALLY VARIABLE TTL DELAY LINE