EPF10K30E - Embedded Programmable Logic Device
Altera 2008/08/06 15:51
General Description
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions.
With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification.
FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.
Table 5 shows FLEX 10KE performance for some common designs.
All performance values were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or chematic design file.
Features
* Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 30,000 to 200,000 typical gates (see Tables 1 and 2)
- Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
* System-level features
- MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
EPF10K50E
EPF10K50S
EPF10K100E
EPF10K130E
EPF10K200E
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions.
With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification.
FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.
Table 5 shows FLEX 10KE performance for some common designs.
All performance values were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or chematic design file.
Features
* Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 30,000 to 200,000 typical gates (see Tables 1 and 2)
- Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
* System-level features
- MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
EPF10K50E
EPF10K50S
EPF10K100E
EPF10K130E
EPF10K200E
EPF10K30E - Embedded Programmable Logic Device
TAG device,
Embedded,
Logic,
programmable
