Description
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family of high-performance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach.
The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required.
The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs.
Reduced component count is inherent with the IMP5111/5112.
The IMP5111/5112 architecture tolerates marginal system designs.
Akey improvement offered by the IMP5111/5112 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance.
Frequently, this situation is not controlled by the peripheral or host designer.
For portable and configurable peripherals, the IMP5111/5112 can be placed in a sleep mode with a disconnect signal.
Quiescent current is less than 275μA when disabled.
When disabled, the outputs are in a high impedance state with output capacitance less than 3pF.

Key Features
*Ultra-Fast response for Fast-20 SCSI applications
*35MHz channel bandwidth
*3.3V operation
*Less than 3pF output capacitance
*Sleep-mode current less than 275μA
*Thermally self limiting
*No external compensation capacitors
*Implements 8-bit or 16-bit (wide) applications
*Compatible with active negation drivers (60mA/channel)
*Compatible with passive and active terminations
*Approved for use with SCSI 1, 2, 3 and UltraSCSI
*Hot swap compatible
*Pin-for-pin compatible with LX5211 and UC5606 (IMP5111)
*Pin-for-pin compatible with LX5212 and UC5603/5613/5614 (IMP5112)

IMP5112
IMP5111CDP  

IMP5111 - 9-Liine SCSII Termiinattor – 35MHz Channell Bandwiidtth

Description
The EM488M1644VBB is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 16 bits.
All inputs and outputs are synchronized with the positive edge of the clock.
The 128Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system.
It also provides auto refresh with power saving / down mode.
All inputs and outputs voltage levels are compatible with LVTTL.
Available packages:TFBGA-54B(8mmx8mm).

Features
* Fully Synchronous to Positive Clock Edge
* Single 2.75V ~ 3.6V Power Supply
* LVTTL Compatible with Multiplexed Address
* Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page
* Programmable CAS Latency (C/L) - 2 or 3
* Data Mask (DQM) for Read / Write Masking
* Programmable Wrap Sequence
- Sequential (B/L = 1/2/4/8/full Page)
- Interleave (B/L = 1/2/4/8)
* Burst Read with Single-bit Write Operation
* All Inputs are Sampled at the Rising Edge of the System Clock
* Auto Refresh and Self Refresh
* 4,096 Refresh Cycles / 64ms (15.625us)

EM488M1644VBB-75F
EM488M1644VBB-7F  

EM488M1644VBB - 128Mb (2M×4Bank×16) Synchronous DRAM

Description
The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) serial paged Flash memories, respectively.
They are accessed by a high speed SPI-compatible bus.
The memories can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction.
The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages.
Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131, 072 bytes.
The memories can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase instruction.
The memory can be write protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on the application needs.
The protection granularity is of 64 Kbytes (sector granularity).

Features
* 1 or 2 Mbit of page-erasable Flash memory
* 2.7 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 75 MHz clock rate (maximum)
* Page size: 256 bytes
- Page Write in 11 ms (typical)
- Page Program in 0.8 ms (typical)
- Page Erase in 10 ms (typical)
* SubSector Erase (32 Kbits)
* Sector Erase (512 Kbits)
* Bulk Erase (1 Mbit for M25PE10, 2 Mbits for M25PE20)
* Deep Power-down mode 1 μA (typical)
* Electronic signature
- JEDEC standard two-byte signature
(8012h for M25PE20, 8011h for M25PE10)
- Unique ID code (UID) with 16 bytes readonly, available upon customer request only in the T9HX process
* Software write protection on a 64-Kbyte sector basis
* More than 100 000 Write cycles
* More than 20 years data retention
* Hardware write protection of the memory area selected using the BP0 and BP1 bits
* Package
- ECOPACK® (RoHS compliant)

M25PE10
M25PE20-VMN6TP
M25PE20-VMP6TP

 

M25PE20 - 1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout