Description
The AV133-315 is a voltage controlled variable attenuator from Alpha’s series of HIP3™ components.
It is specifically designed and specified for use as a wide dynamic range low distortion attenuator for UMTS base station applications centered at 2140 MHz.
The AV133- 315 employs a monolithic quadrature hybrid and a pair of silicon PIN diodes to achieve the specified low distortion performance.
It operates from 0–12 V at 1.6 mA typical control current at maximum attenuation.
The AV133-315 is packaged in a small outline LGA (Land Grid Array) surface mount package with the internal elements affixed to an organic BT substrate.

Features
*23 dB Attenuation Range
*1.5 dB Insertion Loss, 1.5 SWR
*0–12 V Control Voltage
*43 dBm IP3
*Small Footprint LGA Package
*Designed for UMTS Base StationsFeatures
 

AV133-315-HIP3™ Variable Attenuator for UMTS Base Stations

Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively.
Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock.
Programmable burst mode can be used to read up to a full page of data without selecting a
new column address.
The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations.
This provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved).
Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation.
This feature enables flexible performance optimization for a variety of applications.

Features
*PC100/133 compliant
*Organization
-2,097,152 words × 8 bits × 4 banks (8M×8)
-1,048,576 words × 16 bits × 4 banks (4M×16)
*Fully synchronous
-All signals referenced to positive edge of clock
*Four internal banks controlled by BA0/BA1 (bank select)
*High speed
-133/125/100 MHz
-5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
*Low power consumption
-Standby: 7.2 mW max, CMOS I/O
*4096 refresh cycles, 64 ms refresh interval
*Auto refresh and self refresh
*Automatic and direct precharge
*Burst read, single write operation
*Can assert random column address in every cycle
*LVTTL compatible I/O
*3.3V power supply
*JEDEC standard package, pinout and function
-400 mil, 54-pin TSOP II
*Read/write data masking
*Programmable burst length (1/2/4/8/full page)
*Programmable burst sequence (sequential/interleaved)
*Programmable CAS latency (2/3)

AS4LC8M8S0-75TC
AS4LC4M16S0-75TC  

AS4LC8M8S0-3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

Description
The Series STR-F6600 is specifically designed to satisfy the requirements for increased integration and reliability in off-line quasi-resonant flyback converters.
The series incorporates a primary control and drive circuit with discrete avalanche-rated power MOSFETs.
Covering the power range from below 25 watts up to 300 watts for 100/115/230 VAC inputs, and up to 150 watts for 85 to 265 VAC universal input, these devices can be used in a range of applications, from battery chargers and set top boxes, to televisions, monitors, and industrial power supply units.
Cycle-by-cycle current limiting, under-voltage lockout with hysteresis, over-voltage protection, and thermal shutdown protects the power supply during the normal overload and fault conditions.
Over-voltage protection and thermal shutdown are latched after a short delay.
The latch may be reset by cycling the input supply.
Low-current startup and a low-power standby mode selected from the secondary circuit completes a comprehensive suite of features.
The series is provided in a five-pin overmolded TO-3P style package, affording dielectric isolation without compromising thermal characteristics.

FEATURES
*Flyback Operation with Quasi-Resonant Soft Switching
for Low Power Dissipation and EMI
*Rugged Avalanche-Rated MOSFET
*Choice of MOSFET Voltage and rDS(on)
*Full Over-Current Protection (no blanking)
*Under-Voltage Lockout with Hysteresis
*Over-Voltage Protection
*Direct Voltage Feedback
*Low Start-up Current (<400 μA)
*Low-Frequency, Low-Power Standby Operation
*Overmolded 5-Pin Package

 

STR-F6600-OFF-LINE QUASI-RESONANT FLYBACK SWITCHING REGULATORS

DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates.
Electrical erasure of the full memory contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard EPROM and E2PROM devices.
Programming and Erase are performed through an operation and verify algorithm.
The instructions are input via the I/O bus, using a two write cycle scheme.
Address and Data are latched to free the I/O bus and address bus during the write operation.
The CAT28F512 is manufactured using Catalyst’s advanced CMOS floating gate technology.
It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years.
The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages.

FEATURES
*Fast Read Access Time: 90/120/150 ns
*Low Power CMOS Dissipation:
-Active: 30 mA max (CMOS/TTL levels)
-Standby: 1 mA max (TTL levels)
-Standby: 100 mA max (CMOS levels)
*High Speed Programming:
-10 ms per byte
-1 Sec Typ Chip Program
*12.0V ± 5% Programming and Erase Voltage
*Electronic Signature
*Commercial, Industrial and Automotive Temperature Ranges
*Stop Timer for Program/Erase
*On-Chip Address and Data Latches
*JEDEC Standard Pinouts:
-32-pi*DIP
-32-pi*PLCC
-32-pi*TSOP ( 8 x 20)
*100,000 Program/Erase Cycles
*10 Year Data Retention

CAT28F512NI-90T
CAT28F512PI-90T  

CAT28F512 - 512K-Bit CMOS Flash Memory

General Description
The AV9155C-44 is a low cost frequency generator designed specifically for desktop and  notebook PC applications with either 3.3V or 5.0V power supply voltage.
Its CPU clocks provide all necessary CPU frequencies for 286, 386 and 486 systems, including support for the latest speeds of processors.
The device uses a 14.318 MHz crystal to generate the CPU and all peripheral clocks for integrated desktop motherboards.
The dual 14.318 MHz clock outputs allows one output for the system and one to be the input to an ICS graphics frequency generator such as the AV9194.
The CPU clock offers the unique feature of smooth, glitchfree transitions from one frequency to the next, making this ideal device to use whenever slowing the CPU speed.
The AV9155C-44 makes a gradual transition between frequencies, so that it obeys the Intel cycle-to-cycle timing specification for 486 systems.
The simultaneous 2X and 1X CPU clocks offer controlled skew to within 1.5ns (max) of each other.

Features
*Compatible with 286, 386, and 486 CPUs
*Supports turbo modes
*Generates communications clock, keyboard clock, floppy disk clock, system reference clock, bus clock and CPU clock
*Output enable tristates outputs
*Up to 100 MHz at 5V or 3.3V
*20-pin DIP or SOIC
*All loop filter components internal
*Skew-controlled 2X and 1X CPU clocks
*Power-down option

AV9155C-44CW20  

AV9155C-44 - Low Cost 20-Pin Frequency Generator