XC164LM - 16-Bit Single-Chip Microcontroller with C166SV2 Core
Infineon 2008/08/27 09:48
Functional Description
The architecture of the XC164LM combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way.
In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses (see Figure 3-1).
This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC164LM.
The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC164LM.
Summary of Features
* High Performance 16-bit CPU with 5-Stage Pipeline
- 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
- 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
- 1-Cycle Multiply-and-Accumulate (MAC) Instructions
- Enhanced Boolean Bit Manipulation Facilities
- Zero-Cycle Jump Execution
- Additional Instructions to Support HLL and Operating Systems
- Register-Based Design with Multiple Variable Register Banks
- Fast Context Switching Support with Two Additional Local Register Banks
- 16 Mbytes Total Linear Address Space for Code and Data
- 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
* 16-Priority-Level Interrupt System with up to 63 Sources, Sample-Rate down to 50 ns
* 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
* Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
* On-Chip Memory Modules
- 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
- 2 Kbytes On-Chip Data SRAM (DSRAM, XC164LM-8F only)
- 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
- 64 Kbytes (XC164LM-8F) or 32 Kbytes (XC164LM-4F) On-Chip Program Memory (Flash Memory)
* On-Chip Peripheral Modules
- 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
- Multi-Functional General Purpose Timer Unit with 5 Timers
- Two Synchronous/Asynchronous Serial Channels (USARTs)
- Two High-Speed-Synchronous Serial Channels
- On-Chip Real Time Clock, Driven by the Main Oscillator
* Idle, Sleep, and Power Down Modes with Flexible Power Management
* Programmable Watchdog Timer and Oscillator Watchdog
* Up to 47 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
* On-Chip Bootstrap Loader
* On-Chip Debug Support via JTAG Interface
SAF-XC164LM-8F40F
SAF-XC164LM-8F20F
The architecture of the XC164LM combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way.
In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses (see Figure 3-1).
This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC164LM.
The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC164LM.
Summary of Features
* High Performance 16-bit CPU with 5-Stage Pipeline
- 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
- 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
- 1-Cycle Multiply-and-Accumulate (MAC) Instructions
- Enhanced Boolean Bit Manipulation Facilities
- Zero-Cycle Jump Execution
- Additional Instructions to Support HLL and Operating Systems
- Register-Based Design with Multiple Variable Register Banks
- Fast Context Switching Support with Two Additional Local Register Banks
- 16 Mbytes Total Linear Address Space for Code and Data
- 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
* 16-Priority-Level Interrupt System with up to 63 Sources, Sample-Rate down to 50 ns
* 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
* Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
* On-Chip Memory Modules
- 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
- 2 Kbytes On-Chip Data SRAM (DSRAM, XC164LM-8F only)
- 2 Kbytes On-Chip Program/Data SRAM (PSRAM)
- 64 Kbytes (XC164LM-8F) or 32 Kbytes (XC164LM-4F) On-Chip Program Memory (Flash Memory)
* On-Chip Peripheral Modules
- 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
- Multi-Functional General Purpose Timer Unit with 5 Timers
- Two Synchronous/Asynchronous Serial Channels (USARTs)
- Two High-Speed-Synchronous Serial Channels
- On-Chip Real Time Clock, Driven by the Main Oscillator
* Idle, Sleep, and Power Down Modes with Flexible Power Management
* Programmable Watchdog Timer and Oscillator Watchdog
* Up to 47 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
* On-Chip Bootstrap Loader
* On-Chip Debug Support via JTAG Interface
SAF-XC164LM-8F40F
SAF-XC164LM-8F20F
XC164LM - 16-Bit Single-Chip Microcontroller with C166SV2 Core
TAG Chip
