GENERAL DESCRIPTION
The PCnet-ISA+ controller, a single-chip Ethernet controller, is a highly integrated system solution for the,PC-AT Industry Standard Architecture (ISA ) architecture. It is designed to provide flexibility and compatibility with any existing PC application. This highly integrated
132-pin VLSI device is specifically designed to reduce parts count and cost, and addresses applications where higher system throughput is desired. The PCnet-ISA+ controller is fabricated with AMD’s advanced low-power CMOS process to provide low standby current for power sensitive applications.
The PCnet-ISA+ controller is a DMA-based device with a dual architecture that can be configured in two different operating modes to suit a particular PC application. In the Bus Master Mode all transfers are performed using the integrated DMA controller. This configuration enhances system performance by allowing the PCnet-ISA+ controller to bypass the platform DMA controller and directly address the full 24-bit memory space. The implementation of Bus Master Mode allows minimum parts count for the majority of PC applications. The PCnet-ISA+ controller can be configured to perform Shared Memory operations for compatibility with lowend
machines, such as PC/XTs that do not support Bus Master and high-end machines that require local packet buffering for increased system latency.
The PCnet-ISA+ controller is designed to directly interface with the ISA or EISA system bus. It contains an ISA Plug and Play bus interface unit, DMA Buffer Management Unit, 802.3 Media Access Control function, individual 136-byte transmit and 128-byte receive FIFOs, IEEE 802.3 defined Attachment Unit Interface (AUI), and a Twisted Pair Transceiver Media Attachment Unit. The PCnet-ISA+ controller is also register compatible with the LANCE (Am7990) Ethernet controller and PCnet-ISA. The DMA Buffer Management Unit supports the LANCE descriptor software model. External remote boot and Ethernet physical address PROMs and Electrically Erasable Proms are also supported.
This advanced Ethernet controller has the built-in capability of automatically selecting either the AUI port or the Twisted Pair transceiver. Only one interface is active at any one time. The individual 136-byte transmit and 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the embedded General Purpose Serial Interface (GPSI)
allows direct access to/from the MAC. In addition, the device provides programmable on-chip LED drivers for transmit, receive, collision, receive polarity, link integrity and activity, or jabber status. The PCnet-ISA+ controller also provides an External Address Detection Interfaceä (EADIä) to allow external hardware address filtering in internetworking applications.

Am79C98, Am79C100, Am7996, Am79C981, Am79C987, Am79C940, Am79C90, Am79C960, Am79C965, Am79C970
 

AM79C961 - PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller for ISA

GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes.
The 8 bits of data appear on DQ0–DQ7.
The Am29F016D is offered in 48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD) form.
For more information, refer to publication number 21551.
This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply.
A 12.0 volt VPP is not required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.23 μm process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 μm process technology.
The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states.
To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commandsare written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence.
This initiates the Embedded Program algorithm-an internal algorithm that automatically
times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm-an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions.
The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

DISTINCTIVE CHARACTERISTICS
*5.0 V ± 10%, single power supply operation
 -Minimizes system level power requirements
*Manufactured o 0.23 μm process technology
 -Compatible with 0.5 μm Am29F016 and 0.32 μm Am29F016B devices
*High performance
 -Access times as fast as 70 ns
*Low power consumption
 -25 mA typical active read current
 -30 mA typical program/erase current
 -1 μA typical standby current (standard access time to active mode)
*Flexible sector architecture
-32 uniform sectors of 64 Kbytes each
-Any combinatio of sectors ca be erased
-Supports full chip erase
-Group sector protection:
A hardware method of locking sector groups to prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code changes i previously locked sectors
*Embedded Algorithms
-Embedded Erase algorithm automatically preprograms and erases the entire chip or any  combinatio of designated sectors
-Embedded Program algorithm automatically writes and verifies bytes at specified addresses
*Unlock Bypass Program Command
-Reduces overall programming time whe issuing multiple program command sequences
*Minimum 1,000,000 program/erase cycles per sector guaranteed
*20-year data retentio at 125°C
-Reliable operatio for the life of the system
*Package options
-48-pi and 40-pi TSOP
-44-pi SO
-Know Good Die (KGD) (see publicatio number 21551)
*Compatible with JEDEC standards
-Pinout and software compatible with single-power-supply Flash standard
-Superior inadvertent write protection
*Data# Polling and toggle bits
-Provides a software method of detecting program or erase cycle completion
*Ready/Busy# output (RY/BY#)
-Provides a hardware method for detecting program or erase cycle completion
*Erase Suspend/Erase Resume
-Suspends a sector erase operatio to read data from, or program data to, a non-erasing sector,
the resumes the erase operation
*Hardware reset pi(RESET#)
-Resets internal state machine to the read mode

Am29F016D-70FI
Am29F016D-70E4C
Am29F016D-70F4E  

AM29F016D-16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

GENERAL DESCRIPTION
 The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory.
It is organized as 512K bytes, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming.
The device is available in windowed ceramic DIP packages and plastic one-time programmable
(OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states.
The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor system.
AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 100 mW in active mode, and 50 μW in standby mode.
All signals are TTL levels, including programming signals.
Bit locations may be programmed singly, in blocks, or at random.
The device supports AMD’s Flashrite programming algorithm (100 μs pulses) resulting in typical programming time of 1 minute.

DISTINCTIVE CHARACTERISTICS
* Fast access time
- Available in speed options as fast as 90 ns
* Low power consumption
- <10 μA typical CMOS standby current
* JEDEC-approved pinout
- Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
- Easy upgrade from 28-pin JEDEC EPROMs
* Single +5 V power supply
* ±10% power supply tolerance standard
* 100% Flashrite™ programming
- Typical programming time of 1 minute
* Latch-up protected to 100 mA from –1 V to VCC + 1 V
* High noise immunity
* Compact 32-pin DIP, PDIP, PLCC packages

AM27C040-90
AM27C040-120
AM27C040-150
AM27C040-200

 

AM27C040 - 4 Megabit (512 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS
* High-Performance Design
-66-MHz operating frequency
-Frequent instructions execute in one clock
-105.6-million bytes/second burst bus at 33 MHz
-Flexible write-through address control
-Dynamic bus sizing for 8-, 16-, and 32-bit buses
-Soft reset capability
* High On-Chip Integration
-8-Kbyte unified code and data cache
-Floating-point unit
-Paged, virtual memory management
* Enhanced System and Power Management
-Stop clock control for reduced power consumption
-Industry-standard, two-pin System Management Interrupt (SMI) for power management independent of processor operating mode and operating system
-Static design with Auto Halt Power-Down support
-Wide range of chipsets supporting SMM available to allow product differentiation
* Complete 32-Bit Architecture
-Address and data buses
-All registers
-8-, 16-, and 32-bit data types
* Standard Features
-3-V core with 5-V-tolerant I/O
-Binary compatible with all Am486® DX and Am486DX2 microprocessors
-Wide range of support available through the AMDâ FusionE86SM Program
* IEEE 1149.1 JTAG Boundary-Scan Compatibility
* Supports Environmental Protection Agency's Energy Star program
-3-V operation reduces power consumption up to 40%
-Energy management capability provides an excellent base for energy-efficient design
-Works with a variety of energy-efficient, powermanaged devices
* 208-Lead SQFP or 168-Pin PGA Package

GENERAL DESCRIPTION
The Am486DE2 microprocessor is an addition to the AMD Am486 microprocessor family. The Am486DE2 enhances system performance by incorporating flexible clock control and enhanced SMM.
The Am486DE2 CPU clock control feature permits the CPU to be stopped under controlled conditions, allowing reduced power consumption during system inactivity.
The SMM function is implemented with an industry-standard, two-pin interface.

AM486DE2-66V8THC
AM486DE2-66V8TGC

 

AM486DE2 - 8-Kbyte Write-Through Embedded Microprocessor

DISTINCTIVE CHARACTERISTICS
* Member of the E86™ CPU series
– 16-bit data bus
– 24-bit address bus
– 16-Mbyte address range
– Long-term stable supply from AMD
* 40-, 33- and 25-MHz operating speeds
* Ideal for embedded applications
– True Static design for low-power applications
– 3–5 V operation (at 25 MHz)
– Ideal for cost-sensitive designs
– True DC (0 MHz) operation
* Industry Standard Architecture
– Supports world’s largest software base for x86 architectures
– Wide range of chipsets and BIOS available
– Fully compatible with all 386SX systems and software
* System Management Mode (SMM) for system and power management (Am386SXLV only)
– System Management Interrupt (SMI) for power management independent of processor operating mode and operating system
– SMI coupled with I/O instruction break feature provides transparent power off and auto resume of peripherals which may not be “power aware”
– SMI is non-maskable and has higher priority than Non-Maskable Interrupt (NMI)
– Automatic save and restore of the microprocessor state
* 100-lead Plastic Quad Flat Pack (PQFP) package
* Extended temperature version available

GENERAL DESCRIPTION
The Am386®SX/SXL/SXLV microprocessors are lowcost, high-performance CPUs for embedded applications.
Embedded customers benefit from using the Am386 microprocessor in a number of ways.
The Am386SX/SXL/SXLV microprocessors provide embedded customers access to very inexpensive processors and the highest performance of any 386SX available anywhere. The 16-bit data path allows for inexpensive memory design. Full static operation, coupled with 3-V supplies, benefit customers who desire low-power designs. Standby Mode allows the Am386SXL/SXLV microprocessors to be clocked down to 0 MHz (DC) and retain full register contents. A float pin places all outputs in a three-state mode to facilitate board test and debug. Additionally, the Am386SXLV microprocessor comes with System Management Mode (SMM) for system and power management. SMI (System Management Interrupt) is a non-maskable, higher priority interrupt than NMI and has its own code space (1 Mbyte in Real Mode and 16 Mbyte in Protected Mode). SMI can be coupled with the I/O instruction break feature to implement transparent power management of peripherals.
SMM can be used by system designers to implement system and power management code independent of the operating system or the processor mode. Since the Am386SX/SXL/SXLV microprocessors are supported as an embedded product in the E86 family, customers can rely on long-term supply of product, and extended temperature products.
In addition, customers have access to the largest selection of inexpensive development tools, compilers, and chipsets. A large number of PC operating systems and Real Time Operating Systems (RTOS) support the Am386SX/SXL/SXLV microprocessors. This means cheaper development costs, and improved time to market.
The Am386SX/SXL/SXLV microprocessor is available in a small footprint 100-pin Plastic Quad Flat Pack (PQFP) package.

NG80386SX-33
NG80386SX-40

 

NG80386SX-25 - High-Performance, Low-Power, Embedded Microprocessors