GENERAL DESCRIPTION
The AS6C62256 is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.
The AS6C62256 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application.
The AS6C62256 operates with wide range power supply 2.7 ~ 5.5V

FEATURES
*Access time : 55ns
*Low power consumption:
- Operation current : 15mA (TYP.), VCC = 3.0V
- Standby current : 1μA (TYP.), VCC = 3.0V
*Wide range power supply : 2.7 ~ 5.5V
*Fully Compatible with all Competitors 5V product
*Fully Compatible with all Competitors 3.3V product
*Fully static operation
*Tri-state output
*Data retention voltage : 2.0V (MIN.)
*All products ROHS Compliant
*Package : 28-pin 600 mil PDIP, 28-pin 330 mil SOP, 28-pin 8mm x 13.4mm sTSOP

AS6C62256-55PCN, AS6C62256-55SCN, AS6C62256-55SIN, AS6C62256-55STCN
AS6C62256-55STIN  

AS6C62256 - 32K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION
The AS6C6264 is a 65,536-bit low power CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.
The AS6C6264 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application.
The AS6C6264 operates with wide range power supply.

FEATURES
*Access time :55ns
*Low power consumption:
- Operation current : 15mA (TYP.), VCC = 3.0V
- Standby current : 1μA (TYP.), VCC = 3.0V
*Wide range power supply : 2.7 ~ 5.5V
*Fully Compatible with all Competitors 5V product
*Fully Compatible with all Competitors 3.3V product
*Fully static operation
*Tri-state output
*Data retention voltage : 2.0V (MIN.)
*All products ROHS Compliant
*Package : 28-pin 600 mil PDIP, 28-pin 330 mil SOP, 28-pin 8mm x 13.4mm sTSOP

AS6C6264-55PCN, AS6C6264-55SCN, AS6C6264-55SIN, AS6C6264-55STCN, AS6C6264-55STIN  

AS6C6264 - 8K X 8 BIT LOW POWER CMOS SRAM

GENERAL DESCRIPTION
The AS6C4008 is a 4,194,304-bit low power CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature.
The AS6C4008 is well designed for very low power system applications, and particularly well suited for battery back-up non -volatile memory application.
The AS6C4008 operates from a single power supply of 2.7V ~ 5.5V.

FEATURES
*Access time : 55 ns
*Low power consumption:
*Operatingcurrent : 30/20mA (TYP.)
*Standby current : 4μA (TYP.) C-version
*Single 2.7V ~ 5.5V power supply
*Fully static operation
*Tri-state output
*Data retention voltage : 2.0V (MIN.)
*All products ROHS Compliant
*Package :
32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-p:in 600 mil P-DIP
Fully Compatible with all Competitors 5V product
Fully Compatible with all Competitors 3.3V product
32-pin 8mm x 13.4mm sTSOP
36-ball 6mm x 8mm TFBGA
44-pin 8mm x 20mm TSOP-II  

AS6C4008 - 512K X 8 BIT LOW POWER CMOS SRAM

Functional description
The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively.
Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock.
Programmable burst mode can be used to read up to a full page of data without selecting a
new column address.
The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations.
This provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved).
Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation.
This feature enables flexible performance optimization for a variety of applications.

Features
*PC100/133 compliant
*Organization
-2,097,152 words × 8 bits × 4 banks (8M×8)
-1,048,576 words × 16 bits × 4 banks (4M×16)
*Fully synchronous
-All signals referenced to positive edge of clock
*Four internal banks controlled by BA0/BA1 (bank select)
*High speed
-133/125/100 MHz
-5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time
*Low power consumption
-Standby: 7.2 mW max, CMOS I/O
*4096 refresh cycles, 64 ms refresh interval
*Auto refresh and self refresh
*Automatic and direct precharge
*Burst read, single write operation
*Can assert random column address in every cycle
*LVTTL compatible I/O
*3.3V power supply
*JEDEC standard package, pinout and function
-400 mil, 54-pin TSOP II
*Read/write data masking
*Programmable burst length (1/2/4/8/full page)
*Programmable burst sequence (sequential/interleaved)
*Programmable CAS latency (2/3)

AS4LC8M8S0-75TC
AS4LC4M16S0-75TC  

AS4LC8M8S0-3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

GENERAL DESCRIPTION
The AS6C1008 is a 1,048,57 6-bit low power CMOS static random access memory organized as
131,072 words by 8 bits.
It is fabricated using very high performance, high reliability CMO S technology.
Its standby current is stable within the range of operating temperature.
The AS6C1008 is well designed for very low power system applications, and particularly well suited for battery back-up non-volatile memory application.
The AS6C1008 operates from a single power supply of 2.7V ~ 5.5V

FEATURES
* Access time :55ns
* Low power consumption: Operating current:10 mA(TYP.), Standby current: 1 μA(TYP.)
* Single 2.7V ~ 5.5V power supply
* Fully Compatible with all Competitors 5V product
* Fully Compatible with all Competitors 3.3V product
* Fully static operation
* Tri-state output
* Data retention voltage : 1.5V (MIN.)
* All products are ROHS Compliant
* Package :
- 32-pin 450 mil SOP
- 32-pin 600 mil P-DIP
- 32-pin 8mm x 20mm TSOP-I
- 32-pin 8mm x 13.4mm sTSOP
- 36-ball 6mm x 8mm TFBGA

 

AS6C1008 - 128K X 8 BIT LOW POWER CMOS SRAM