FEATURES
USB 2.0 (480 Mbps) and USB 1.1 (12 Mbps) signal switching compliant Tiny 10-lead 1.6 mm × 1.3 mm mini LFCSP package and 12-lead 3 mm × 3 mm LFCSP package 2.7 V to 3.6 V single-supply operation Typical power consumption: <0.1 μW RoHS compliant

APPLICATIONS
USB 2.0 signal switching circuits
Cellular phones
PDAs
MP3 players
Battery-powered systems
Headphone switching
Audio and video signal routing
Communications systems

GENERAL DESCRIPTION
The ADG772 is a low voltage, CMOS device that contains two independently selectable single-pole, double throw (SPDT) switches. It is designed as a general-purpose switch and can be used for routing both USB 1.1 and USB 2.0 signals.
This device offers a data rate of 1260 Mbps, making the part suitable for high frequency data switching. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG772 exhibits break-before-make switching action.
The ADG772 comes in a 12-lead LFCSP, and a 10-lead mini LFCSP. These packages make the ADG772 the ideal solution for space-constrained applications.

PRODUCT HIGHLIGHTS
1. 1.6 mm × 1.3 mm mini LFCSP package.
2. USB 1.1 (12 Mbps) and USB 2.0 (480 Mbps) compliant.
3. Single 2.7 V to 3.6 V operation.
4. RoHS compliant.
TAG CMOS, dual, USB

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FEATURES
General
Low-power HDMITM/DVI transmitter ideal for portable applications CEC controller and buffer reduces system overhead.
Compatible with HDMI v1.3, DVI v1.0, and HDCP 1.3 Single 1.8V power supply Video/audio inputs accept logic level s from 1.8V to 3.3V Digital video 80 MHz operation supports all video resolutions from 480i to 1080i Programmable two-way color space converter Supports RGB, YCbCr, DDR Supports ITU656 based embedded syncs Auto input video format timing detection (CEA-861D) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel uncompressed LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU with I2C® master to perform HDCP operations and EDID reading operations 5 V tolerant I2C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S On-chip MPU reports HDMI events through interrupts and registers

APPLICATIONS
Digital video cameras,
Digital still cameras
Personal media players
Cellular handsets
DVD players and recorders
Digital set-top boxes
A/V receivers
HDMI repeater

GENERAL DESCRIPTION
The ADV7520NK is an 80 MHz, high definition multimedia interface (HDMI) v.1.3 transmitter. It supports HDTV formats up to 1080i and 720p, and computer graphic resolutions up to XGA (1024 x 768 @ 75 Hz). With the inclusion of HDCP (available in the BGA package only), the ADV7520NK allows the secure transmission of protected content as specified by the HDCP v1.3 protocol.
The ADV7520NK supports both S/PDIF and 8-channel I2S audio. Its high fidelity 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio including Dolby® Digital and DTS®.
The ADV7520NK helps to reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I2C master for EDID reading, a single
1.8V power supply and 5 V tolerance on I2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the ADV7520NK is available in a space saving, 76-ball, CSP_BGA or 64-lead LFCSP surface-mount package. Both packages are available as
RoHS compliant and are specified from −25°C to +85°C operational.

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FEATURES
RF transceiver with integrated ADCs and DACs
IEEE 802.16 WiMAX/WiBro
2.3 GHz to 2.7 GHz
3.5 MHz < BW < 20 MHz
Superior receiver sensitivity with NF 3.7 dB
Highly linear and spectrally pure transmitter
Tx EVM −38 dB
SNR > 134 dB/Hz at FOFFSET > 22 MHz
Tx power control
Range: 0 dB to 58 dB
Resolution: 0.25 dB
Autonomous AGC and Tx power control
Automatic frequency correction < 0.012 ppm
Integrated Frac-N synthesizer
8 Hz LO step size
Integrated phase noise < 0.4°rms
APPLICATIONS
WiMAX/WiBro/BWA

GENERAL DESCRIPTION
The AD9352 is a fully integrated transceiver for IEEE 802.16 WiMAX and WiBro wireless network systems. The RF MxFE™ combines the RF front-end with mixed-signal baseband enabling an easy-to-use digital interface to the baseband ASIC or FPGA. The AD9352 operates in the 2.3 GHz to 2.7 GHz range covering most of the licensed and unlicensed bands. Channel bandwidths of 3.5 MHz, 4.375 MHz, 5 MHz, 7 MHz, 8.75 MHz, 10 MHz, 14 MHz, 17.5 MHz, and 20 MHz are supported.
The direct-conversion receiver has state-of-the-art noise figure and linearity and requires no external components with the exception of a balun. The complete RF subsystem integrates an autonomous AGC loop and dc offset corrections, thus elimi-nating the need for high speed interaction with the baseband processor. The received signal strength indicator (RSSI) has over 80 dB of dynamic range with 0.5 dB resolution and is accessible via the serial interface.
The received signal is digitized with a high dynamic range 12-bit ADC. Decimation and channel filters produce a 10-bit output signal at the appropriate sample rate determined by the bandwidth mode. The transmit path takes a 10-bit input data and interpolates before converting to the analog domain and upconverting to the carrier frequency.
The highly linear transmit path has excellent spectral purity with sideband noise less than −134 dBc/Hz at 22 MHz offset and offers EVM of −38 dB at 0 dBm output power. The transmit power is detected by an accurate power detector and autono-mously controlled with a range of 58 dB and 0.25 dB steps. The output power can be calibrated at the factory by a single meas-urement.
The reference frequency is produced by an internal crystal oscillator with a digital programmable frequency with 0.012 ppm resolution thus reducing the total bill of materials of the device.
An internal auxiliary ADC and two auxiliary DACs are avail-able for system monitoring and control. Three general purpose I/Os are also included and can be register programmed or auto-matically sequenced by a user-defined state machine. Mode control is via a 4-wire serial port and four real-time I/O control pins.
The AD9352 is powered from a single 3.3 V supply and contains on-chip LDOs for each function to eliminate external regula-tors. The AD9352 is packaged in a 9 mm × 9 mm, 64-lead LFCSP.

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FEATURES
General
* HDMI™/DVI transmitter compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2
* Internal key storage for HDCP
* Single 1.8 V power supply
* Video/audio inputs accept logic levels from 1.8 V to 3.3 V
* 80-lead LQFP, Pb-free package
* 64-lead LFCSP, Pb-free package
Digital video
* 165 MHz operation supports all resolutions from 480i to 1080p and UXGA at 60 Hz
* Programmable two-way color space converter
* Supports RGB, YCbCr, and DDR
* Supports ITU656-based embedded syncs
* Automatic input video format timing detection (CEA-861B) Digital audio
* Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel, uncompressed, LPCM I2S audio up to 192 kHz
* Special features for easy system design
- On-chip MPU with I2C® master to perform HDCP operations and EDID reading operations
- 5 V tolerant I2C and HPD I/Os, no extra device needed
- No audio master clock needed for supporting S/PDIF and I2S
- On-chip MPU reports HDMI events through interrupts and registers

APPLICATIONS
* DVD players and recorders
* Digital set-top boxes
* A/V receivers
* Digital cameras and camcorders
* HDMI repeater/splitter

GENERAL DESCRIPTION
 The AD9389B is a 165 MHz, high definition multimedia inter-face (HDMI) v. 1.3 transmitter. It supports HDTV formats up to 1080p, and computer graphic resolutions up to UXGA (1600 × 1200 @ 60 Hz). With the inclusion of HDCP, the AD9389B allows the secure transmission of protected content as specified by the HDCP v. 1.2 protocol.
 The AD9389B supports both S/PDIF and 8-channel I2S audio. Its high fidelity, 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio, including DTS®, THX®, and Dolby® Digital.
 The AD9389B helps reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I2C master for EDID reading, a single 1.8 V power supply, and 5 V tolerance on the I2C and hot plug detect pins.
 Fabricated in an advanced CMOS process, the AD9389B is available in a space-saving, 64-lead LFCSP surface-mount package, and an 80-lead LQFP surface-mount package. All packages are available as Pb-free and are specified from −25°C to +85°C.

AD9389BBCPZ-80
AD9389BBCPZ-165
AD9389BBSTZ-80
AD9389BBSTZ-165
AD9389B/PCB

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FEATURES
- 6-Phase Vertical Transfer Clock Support
- Correlated Double Sampler (CDS)
- 6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA)
- 12-Bit 36 MHz A/D Converter
- Black Level Clamp with Variable Level Control
- Complete On-Chip Timing Generator
- Precision Timing Core with <600 ps Resolution
- On-Chip 3 V Horizontal and RG Drivers
- 2-Phase and 4-Phase H-Clock Modes
- Electronic and Mechanical Shutter Modes
- On-Chip Driver for External Crystal
- On-Chip Sync Generator with External Sync Input
- 56-Lead LFCSP Package

APPLICATIONS
- Digital Still Cameras
- Digital Video Camcorders
- Industrial Imaging

GENERAL DESCRIPTION
 The AD9995 is a highly integrated CCD signal processor for digital still camera and camcorder applications. It includes a complete analog front end with A/D conversion, combined with a
full-function programmable timing generator. The timing generator is capable of supporting both 4- and 6-phase vertical clocking. A Precision Timing core allows adjustment of high speed clocks with less than 600 ps resolution at 36 MHz operation.

 The AD9995 is specified at pixel rates of up to 36 MHz. The analog front end includes black level clamping, CDS, VGA, and a 12-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving 56-lead LFCSP, the AD9995 is specified over an operating temperature range of –20°C to +85°C.

AD9995KCP
AD9995KCPRL

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FEATURES
* Low cost, 3.3 V CMOS MxFE® for broadband modems
* 10-bit digital-to-analog converter (DAC)
- 2×/4× interpolation filter
- 250 MSPS DAC update rate
* 10-bit, 75 MSPS ADC
* Low noise RxPGA
- Dual channel muxed input
- 6 dB input overload attenuator
−12 dB to +48 dB (without attenuator)
* Third-order programmable low-pass filter
* Flexible digital datapath interface
- Half-duplex and full-duplex operation
- Programmable delay Tx driver disable signal
* Various power-down/reduction modes
* Internal clock multiplier (PLL)
* 2 auxiliary programmable clock outputs
* 64-lead LFCSP

APPLICATIONS
Power-line networking

GENERAL DESCRIPTION
 The AD9867 is a mixed-signal front-end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 75 MSPS. Its flexible digital interface, power-saving modes, and high Tx-to-Rx isolation make the part well suited for half-duplex and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends. Power-saving modes can reduce power consumption of individual functional blocks or can power down unused blocks in half-duplex applications.

 A serial port interface (SPI®) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source.

 The Tx signal path consists of a bypassable 2×/4× low-pass interpolation filter and a 10-bit, 250 MSPS TxDAC. The transmit path signal bandwidth can be as high as 33.6 MHz at an input data rate of 75 MSPS. The TxDAC provides differential current outputs that can be steered directly to a differential or single-ended external load. Tx power can be digitally controlled over a 7.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit analog-to-digital converter (ADC). The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3.6 nV/√Hz for gain settings beyond 36 dB. An optional attenuator provides an additional 6 dB (or more) of attenuation (when combined with external series resistors).
 
 The receive path LPF cutoff frequency can either be set over a 22 MHz to 38 MHz range or simply bypassed. The 10-bit ADC achieves excellent dynamic performance over a 5 MSPS to 75 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.
 The AD9867 provides a highly integrated solution for broadband modems. It is available in a space-saving, 64-lead LFCSP and is specified over the commercial (−40°C to +85°C) temperature range.
TAG Modem, SIGNAL

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FEATURES
1. GSPS internal clock speed (up to 400 MHz out directly)
- Integrated 1 GSPS 14-bit DAC
- 48-bit frequency tuning word
- Differential HSTL Comparator
- Flexible System Clock Input accepts either crystal or external reference clock.
- On-chip Low-Noise PLL REFCLK Multiplier
2. Spur Reduction Channels
- Low Jitter clock doubler for frequencies up to 750 MHz
- Single-ended CMOS Comparator; frequencies < 50MHz
- Programmable output divider for CMOS output
- Serial I/O control
- Excellent Dynamic Performance
- Software controlled power-down
- 64-lead LFCSP package
- Phase Noise @ 95MHz using Vectron VCC6 87.5MHz Oscillator:
100 Hz Offset: -103 dBc/Hz
10 kHz Offset: -133 dBc/Hz
1 MHz Offset: -136 dBc/Hz

APPLICATIONS
- Agile LO frequency synthesis
- Low jitter, fine tune clock generation
- Test and measurement equipment
- Wireless Base Stations, Controllers
- Secure Communications
- Fast frequency hopping

GENERAL DESCRIPTION
 The AD9912 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC. The AD9912 features a 48–bit frequency tuning word (FTW) which can synthesize frequencies in step sizes no larger than 4 uHz. Absolute frequency accuracy can be achieved by adjusting the DAC
system clock.
 
 The AD9912 also features an integrated system clock PLL, which allows reference clocks as low as 25 MHz. The AD9912 operates over an industrial temperature range, spanning -40°C to +85°C.

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FEATURES
- 12 MSPS Correlated Double Sampler (CDS)
- 10-Bit 12 MHz A/D Converter
- No Missing Codes Guaranteed
- 6 dB to 40 dB Variable Gain Amplifier (VGA)
- Black Level Clamp with Variable Level Control
- Complete On-Chip Timing Generator
- Precision Timing Core with 1.7 ns Resolution
- On-Chip: 6-Channel Horizontal and 1-Channel RS Drivers
- 4-Phase Vertical Transfer Clocks
- Electronic and Mechanical Shutter Modes
- On-Chip Sync Generator with External Sync Option

APPLICATIONS
- Digital Still Cameras
- Industrial Imaging

GENERAL DESCRIPTION
The AD9937 is a highly integrated CCD signal processor. It includes a complete analog front end with A/D conversion, combined with a full-function programmable timing generator.
A Precision Timing core allows adjustment of high speed clocks with 1.7 ns resolution at 12 MHz operation.

 The AD9937 is specified at pixel rates of up to 12 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RS, H-clocks, V-clocks, sensor gate pulses, and substrate charge reset pulse. Operation is programmed using a 3-wire serial interface.
The AD9937 is packaged in a 56-lead LFCSP and specified over an operating temperature range of –25°C to +85°C.

AD9937KCP
AD9937KCPRL

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FEATURES

New AD9949A supports CCD line length > 4096 pixels
Correlated double sampler (CDS)
0 dB to 18 dB pixel gain amplifier (PxGA®)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit, 36 MSPS analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing driver
Precision Timing™ core with < 600 ps resolution
On-chip 3 V horizontal and RG drivers
40-lead LFCSP package


APPLICATIONS
Digital still cameras
High speed digital imaging applications

GENERAL DESCRIPTION
 The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution.

 The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface.
 
 Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of 20°C to +85°C.

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FEATURES
* Complete 8-Bit DAC
* Voltage Output—0 V to 2.56 V
* Internal Precision Band-Gap Reference
* Single-Supply Operation: 5 V (10%)
* Full Microprocessor Interface
* Fast: 1 s Voltage Settling to 1/2 LSB
* Low Power: 75 mW
* No User Trims Required
* Guaranteed Monotonic Over Temperature
* All Errors Specified TMIN to TMAX
* Small 16-Lead DIP or 20-Lead PLCC Package
* Low Cost

PRODUCT DESCRIPTION
 The AD557 DACPORT® is a complete voltage-output 8-bit digital-to-analog converter, including output amplifier, full microprocessor interface and precision voltage reference on a single monolithic chip. No external components or trims are required to interface, with full accuracy, an 8-bit data bus to an analog system.
 
 The low cost and versatility of the AD557 DACPORT are the result of continued development in monolithic bipolar technologies. The complete microprocessor interface and control logic is implemented with integrated injection logic (I2L), an extremely dense and low-power logic structure that is process-compatible with linear bipolar fabrication. The internal precision voltage reference is the patented low-voltage band-gap circuit which permits full-accuracy performance on a single 5 V power supply.

 Thin-film silicon-chromium resistors provide the stability required for guaranteed monotonic operation over the entire operating temperature range, while laser-wafer trimming of these thin-film resistors permits absolute calibration at the factory to within ± 2.5 LSB; thus, no user-trims for gain or offset are required. A new circuit design provides voltage settling to ±1/2 LSB for a
full-scale step in 800 ns.

 The AD557 is available in two package configurations. The AD557JN is packaged in a 16-lead plastic, 0.3"-wide DIP. For surface mount applications, the AD557JP is packaged in a 20-lead JEDEC-standard PLCC. Both versions are specified over the operating temperature range of 0°C to 70°C.

PRODUCT HIGHLIGHTS
 1. The 8-bit I2L input register and fully microprocessorcompatible control logic allow the AD557 to be directly connected to 8- or 16-bit data buses and operated with standard control signals. The latch may be disabled for direct DAC interfacing.
 2. The laser-trimmed on-chip SiCr thin-film resistors are calibrated for absolute accuracy and linearity at the factory. Therefore, no user trims are necessary for full rated accuracy over the operating temperature range.
 3. The inclusion of a precision low-voltage band-gap reference eliminates the need to specify and apply a separate reference source.
 4. The AD557 is designed and specified to operate from a single 4.5 V to 5.5 V power supply.
 5. Low digital input currents, 100 µA max, minimize bus loading. Input thresholds are TTL/low voltage CMOS compatible.
 6. The single-chip, low power I2L design of the AD557 is inherently more reliable than hybrid multichip or conventional single-chip bipolar designs.

AD557JN AD557JP
TAG bit, DAC, low

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