Description
Designed specifically to address high-end embedded applications for storage, the PowerPC 440SP Embedded Processor (PPC440SP) provides a highperformance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation.
This chip contains a high-performance RISC processor core, a DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three DDR PCI-X bus interfaces, an Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O.

Features
*PowerPC‚ 440 processor core operating at up to 667MHz with 32-KB I- and D-caches (with parity checking)
*On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory
*Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details)
*Supports up to 4 GB (2 Chip Selects) of 64-bit/32-bit SDRAM with ECC
– DDR1 266-333-400
– DDR2 400-533-667
*Three DDR PCI-X interfaces (32-bit or 64-bit) up to 133 MHz (DDR 266) with support for
conventional PCI
*XOR Accelerator with DMA controller
*Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P &
Q parity computations, supports up to 255 drives
*I2O Messaging Unit with two DMA controllers
*External Peripheral Bus (24-bit Address, 8-bit Data) for up to three devices
*One Ethernet 10/100/1000 Mbps half- or fullduplex interface. Operational modes supported
are MII and GMII.
*Programmable Interrupt Controller supports interrupts from a variety of sources.
*Programmable General Purpose Timers (GPT)
*Three serial ports (16750 compatible UART)
*Two IIC interfaces
*General Purpose I/O (GPIO) interface available
*JTAG interface for board level testing
*Processor can boot from PCI memory

PPC440SP, PPC440SP-AFC533C, PPC440SP-RFC533C  

440SP - PowerPC 440SP Embedded Processor

Description
The S19250 MUX/DeMux chip is a fully integrated serialization/de-serialization SONET STS-192/10 GB Ethernet/Fiber Channel transceiver with Electronic Dispersion Compensation (EDC).
This device can be used to compensate channel impairments caused by Single Mode Fiber (SMF) and copper medium.
The chip performs all necessary parallel-to-serial and serial-to-parallel functions in onformance
with SONET/SDH, 10 Gigabit Ethernet (10 GbE) and 10 Gigabit Fibre Channel (10 G FC) transmission standards.
The figure below shows a typical network application.
The other application block diagrams are shown on page 2.
On-chip clock synthesis PLL components are contained in the S19250 chip, allowing the use
of a slower external transmit clock reference.
The chip can be used with 155.52 MHz or 622.08 MHz (or equivalent FEC/10 GbE/10 G FC rates) reference clocks, in support of existing system clocking schemes.
The low-jitter LVDS interface guarantees compliance with the biterror rate requirements of the Telcordia and ITUT standards.

Features
*Operational from 9.9 Gbps to 11.3 Gbps
*Built-In Self Test (BIST) with Error Counter
*On-chip High-Frequency PLLs for Clock Recovery and Clock Gen.
*16-bit LVDS Parallel Data Path
*TX and RX Lock Detect Indicators
*Reference Loop Timing Modes
*Line and Diagnostic Loopback Mode for Faulty Node Identification
*-40°C to 85°C Industrial Temperature Range
*Supports MDIO, I2C and SPI serial interface
*Complies with applicable OIF SFI-4 Phase 1, Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae
and XFP MSA Standards
*2000 V ESD rating on low speed pins, 1000 V on high speed I/Os
*17 x 17 mm2, 1.0 mm pitch package with Green / RoHS compliant lead free option. Pin Compatible with S19235/S19237.
*1.1 W typical

Applications
*SONET/SDH and 10GbE-Based Transmission Systems & Modules
*Section Repeaters
*Add Drop Multiplexers (ADM)
*Broad-Band Cross-Connects
*Fiber Optic Test Equipment

 

S19250 - 16-bit Transceiver with EDC

Description
Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements.
This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-12E, 0.25 μm (0.18 μm Leff)
Package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (E-PBGA)
Power (typical): TBDW at 133MHz, 1.5W at 200MHz, 2W at 266MHz

Features
* PowerPC® 405 32-bit RISC processor core operating up to 266MHz
* Synchronous DRAM (SDRAM) interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
* 4KB on-chip memory (OCM)
* External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and external peripherals
- Up to eight devices
- External Mastering supported
* DMA support for external peripherals, internal UART and memory
- Scatter-gather chaining supported
- Four channels
* PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
- Synchronous or asynchronous PCI Bus interface
- Internal or external PCI Bus Arbiter
* Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII)
* Programmable interrupt controller supports seven external and 19 internal edge triggered or levelsensitive interrupts
* Programmable timers
* Two serial ports (16550 compatible UART)
* One IIC interface
* General purpose I/O (GPIO) available
* Supports JTAG for board level testing
* Internal processor local Bus (PLB) runs at SDRAM interface frequency
* Supports PowerPC processor boot from PCI memory  

405GP - Power PC 405GP Embedded Processor

GENERAL DESCRIPTION
 The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment.
The S3029 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock.
The chip outputs a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO).
The phase detector compares the phase relationship between the VCO output and the serial data input.
A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage.
A block diagram is shown in Figure 2.
There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input.

FEATURES
* Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation
* Five on-chip high frequency PLLs with internal loop filters for clock recovery
* Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data
* Clock Multiplier PLL for transmit clock generation
* 19.44 or 51.84 MHz reference frequency
* Lock detect—monitors run length and frequency
* Low-jitter differential interface
* 3.3V supply
* Available in a 64-pin TQFP package
* Compatible with IgT WAC-413 ATM Quad- UNI processor

S3029A

 

S3029 - SONET/SDH/ATM 155 MBIT/S QUAD TRANSCEIVER