DESCRIPTION
The AZ10/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 is ideally suited for those applications that require the ultimate in AC performance.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*230ps Propagation Delay
*High Bandwidth Output Transitions
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semiconductor MC10EL01 & MC100EL01

AZ100EL01  

AZ10EL01 - ECL/PECL 4-Input OR/NOR

DESCRIPTION
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*700 MHz Minimum Shift Frequency
*9-Bit for Byte-Parity Application
*Asynchronous Master Reset
*Dual Clocks
*Operating Range of 4.2V to 5.46V
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semi MC10E142 & MC100E142

AZ100E142, AZ10E142FN, AZ100E142FN
 

AZ10E142-ECL/PECL 9-bit Shift Register

DESCRIPTION
The AZ10/100LVEL11 is a differential 1:2 fanout gate.
The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open input conditions.
If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*265ps Propagation Delay
*5ps Skew Between Outputs
*High Bandwidth Output Transitions
*Internal Input Pulldown Resistors
*Operating Range of 3.0V to 5.5V
*Direct Replacement for ON Semi
-MC100LVEL11, MC10EL11
-& MC100EL11
*Transistor Count = 51

AZ100LVEL11

 

AZ10LVEL11 - ECL/PECL 1:2 Differential Fanout Buffer

DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs.
Each flip-flop may be locked separately by holding Common Clock (CC) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using CC to clock all four flip-flops.
In this case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn).
Asynchronous set controls (Sn) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and C¯¯En are LOW, and transfers to the slave when either CC or C¯¯En (or both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
* 1100 MHz Min. Toggle Frequency
* Differential Outputs
* Individual and Common Clocks
* Individual Resets (asynchronous)
* Paired Sets (asynchronous)
* Operating Range of 4.2V to 5.46V
* 75kΩ Internal Input Pulldown Resistors
* Direct Replacement for On Semiconductor MC10E131 & MC100E131  

AZ10E131 - ECL/PECL 4-bit D Flip-Flop

DESCRIPTION
The AZ10/100ELT22 is a dual CMOS/TTL to differential PECL translator.
Because PECL (Positive ECL) levels are used, only VCC and ground are required.
The small outline packaging and the low skew, dual gate design of the ELT22 makes it ideal for applications that require the translation of a clock and a data signal.
The ELT22 is available in both PECL standards: the 10ELT is compatible with PECL 10K logic levels while the 100ELT is compatible with PECL 100K logic levels.
NOTE: Specifications in PECL tables are valid when thermal equilibrium is established.

FEATURES
* Green / RoHS Compliant / Lead (Pb) Free package available
* 0.5ns Typical Propagation Delay
* <100ps Typical Output to Output Skew
* Differential PECL Outputs
* Flow Through Pinouts
* Operating Range of 3.0V to 5.5V
* Direct Replacement for ON Semiconductor MC10ELT22, MC100ELT22, MC100LVELT22 & Micrel SY89322V
* IBIS Model Files Available on Arizona Microtek Website

AZ100ELT22
AZ10ELT22D
AZ100ELT22D
AZ100ELT22DG
AZ100ELT22T
AZ100ELT22TG  

AZ10ELT22 - CMOS/TTL to Differential PECL Translator