Article List :  Cypress : 11 posted

CY7C601XX - enCoRe™ II Low Voltage Microcontroller

Cypress 2009/01/03 10:37

Introduction
The enCoRe II LV family brings the features and benefits of the enCoRe II to non USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wakeup circuitry, are also integrated into this chip.
The enCoRe II LV is a low voltage, low cost 8-bit Flash programmable microcontroller.
The enCoRe II LV features up to 36 GPIO pins. The IO pins are grouped into five ports (Port 0 to 4). The pins on Ports 0 and 1 are configured individually, when the pins on Ports 2, 3, and 4
are only configured as a group. Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output with up to five pins that
support programmable drive strength of up to 50 mA sink current. Additionally, each IO pin is used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has, in addition to the port interrupt vector, three dedicated pins that have independent interrupt vectors (P0.2–P0.4).
The enCoRe II LV features an internal oscillator. Optionally, an external 1 MHz to 24 MHz crystal is used to provide a higher precision reference. The enCoRe II LV also supports external clock.
The enCoRe II LV has 8 Kbytes of Flash for user code and 256 bytes of RAM for stack space and user variables.
In addition, enCoRe II LV includes a watchdog timer, a vectored interrupt controller, a 16-bit free running timer with capture registers, and a 12-bit programmable interval timer. The power
on reset circuit detects when power is applied to the device, resets the logic to a known state, and executes instructions at Flash address 0x0000. When power falls below a programmable
trip voltage, it generates a reset or is configured to generate an interrupt. There is a low voltage detect circuit that detects when VCC drops below a programmable trip voltage. This is configurable to generate a LVD interrupt to inform the processor about the low voltage event. POR and LVD share the same interrupt; there is no separate interrupt for each. The watchdog timer ensures the firmware never gets stalled in an infinite loop.
The microcontroller supports 17 maskable interrupts in the vectored interrupt controller. All interrupts can be masked. Interrupt sources include LVR or POR, a programmable interval
timer, a nominal 1.024 ms programmable output from the free running timer, two capture timers, five GPIO ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, and an internal
wakeup timer interrupt. The wakeup timer causes periodic interrupts when enabled. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge-sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling.
The free running timer generates an interrupt at 1024 μs rate. It also generates an interrupt when the free running counter overflow occurs—every 16.384 ms. The duration of an event
under firmware control is measured by reading the timer at the start and end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers
save a programmable 8-bit range of the free running timer when a GPIO edge occurs on the two capture pins (P0.5 and P0.6). The two 8-bit capture registers are ganged into a single 16-bit
capture register.
The enCoRe II LV supports in-system programming by using the P1.0 and P1.1 pins as the serial programming mode interface.

Features
*enCoRe™ II Low Voltage (enCoRe II LV)—enhanced component reduction
- Internal crystalless oscillator with support for optional external clock or external crystal or resonator
- Configurable IO for real world interface without external components
*Enhanced 8-bit microcontroller
- Harvard architecture
- M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal
*Internal memory
- 256 bytes of RAM
- 8 Kbytes of Flash including EEROM emulation
*Low power consumption
- Typically 2.25 mA at 3 MHz
- 5 μA sleep
*In-system reprogrammability
- Allows easy firmware update
*General purpose IO ports
- Up to 36 General Purpose IO (GPIO) pins
- 2 mA source current on all GPIO pins. Configurable 8 or 50 mA per pin current sink on designated pins
- Each GPIO port supports high impedance inputs, configurable pull up, open drain output, CMOS and TTL inputs, and CMOS output
- Maskable interrupts on all IO pins
*SPI serial communication
- Master or slave operation
- Configurable up to 2 Mbit per second transfers
- Supports half duplex single data line mode for optical sensors
*2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge times
- Two registers each for two input pins
- Separate registers for rising and falling edge capture
- Simplifies interface to RF inputs for wireless applications
*Internal low power wakeup timer during suspend mode
- Periodic wakeup with no external components
*Programmable interval timer interrupts
*Reduced RF emissions at 27 MHz and 96 MHz
*Watchdog timer (WDT)
*Low voltage detection with user selectable threshold voltages
*Improved output drivers to reduce EMI
*Operating voltage from 2.7V to 3.6V DC
*Operating temperature from 0–70°C
*Available in 24 and 40-pin PDIP, 24-pin SOIC, 24-pin QSOP and SSOP, 28-pin SSOP, and 48-pin SSOP
*Advanced development tools based on Cypress PSoC® tools
*Industry standard programmer support

Applications
The CY7C601xx and CY7C602xx are targeted for the following applications:
*PC wireless HID devices
- Mice (optomechanical, optical, trackball)
- Keyboards
- Presenter tools
*Gaming
- Joysticks
- Gamepad
*General purpose wireless applications
- Remote controls
- Barcode scanners
- POS terminal
- Consumer electronics
- Toys

CY7C602xx, CY7C60123-PVXC, CY7C60123-PXC, CY7C60113-PVXC,
CY7C60223-PXC, CY7C60223-SXC, CY7C60223-QXC
 

CY7C601XX - enCoRe™ II Low Voltage Microcontroller

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CYWB0124AB - West Bridge™ : Antioch™ USB/Mass Storage Peripheral Controller

Cypress 2008/11/11 09:24

Features
*SLIM™ Architecture, allowing simultaneous and independent data paths between Processor & USB and between USB & Mass Storage
*High-Speed USB at 480 Mbps
- USB 2.0 compliant
- Integrated USB 2.0 transceiver, smart Serial Interface Engine
- 16 programmable endpoints
*Mass Storage device support
- MMC/MMC+/SD
- NAND flash: x8 or x16, SLC
- Full NAND management (ECC, wear-leveling)
*Memory-mapped interface to main processor
*DMA slave support
*Ultra low-power, 1.8V core operation
*Low Power Modes
*Small footprint, 6x6mm VFBGA
*Selectable Clock Input Frequencies
- 19.2 MHz, 24 MHz, 26 MHz, 48 MHz

Applications
*Cellular Phones
*Portable Media Players
*Personal Digital Assistants
*Digital Cameras
*Portable Video Recorder  

CYWB0124AB - West Bridge™ : Antioch™ USB/Mass Storage Peripheral Controller

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CY2SSTV850 - Differential Clock Buffer/Driver

Cypress 2008/09/19 09:30

Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks.

Features
*Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
*1:10 differential outputs
*External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input
*SSCG: Spread Aware™ for EMI reduction
*48-pin SSOP and TSSOP packages
*Conforms to JEDEC JC40 and JC42.5 DDR specifications

CY2SSTV850OC, CY2SSTV850OCT, CY2SSTV850ZC, CY2SSTV850ZCT  

CY2SSTV850 - Differential Clock Buffer/Driver

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W320-03 - 200-MHz Spread Spectrum Clock Synthesizer/Driver

Cypress 2008/08/02 10:11

Features
* Compliant with Intel® CK-Titan Clock Synthesizer/Driver Specifications
* Multiple output clocks at different frequencies
* Three pairs of differential CPU outputs, up to 200 MHz
* Ten synchronous PCI clocks, three free-running
* Six 3V66 clocks
* Two 48-MHz clocks
* One reference clock at 14.318 MHz
* One VCH clock
* Spread Spectrum clocking (down spread)
* Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#)
* Three Select inputs (Mode select & IC Frequency Select)
* OE and Test Mode support
* 56-pin SSOP package and 56-pin TSSOP package

Benefits
* Supports next-generation Pentium® processors using differential clock drivers
* Motherboard clock generator
* Support Multiple CPUs and a chipset
* Support for PCI slots and chipset
* Supports AGP, DRCG reference and Hub Link
* Supports USB host controller and graphic controller
* Supports ISA slots and I/O chip
* Enables reduction of electromagnetic interference (EMI) and overall system cost
* Enables ACPI-compliant designs
* Supports up to four CPU clock frequencies
* Enables ATE and “bed of nails” testing
* Widely available, standard package enables lower cost

W320-03H
W320-03HT
W320-03X
W320-03XT

 

W320-03 - 200-MHz Spread Spectrum Clock Synthesizer/Driver

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W320-04 - 200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

Cypress 2008/07/04 09:28

Features
* Compliant with Intel® CK-Titan clock synthesizer/driver specifications
* Multiple output clocks at different frequencies
- Three pairs of differential CPU outputs, up to 200 MHz
- Ten synchronous PCI clocks, three free-running
- Six 3V66 clocks
- Two 48-MHz clocks
- One reference clock at 14.318 MHz
- One VCH clock
* Spread Spectrum clocking (down spread)
* Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#)
* Three Select inputs (Mode select and IC Frequency Select)
* OE and Test Mode support
* 56-pin SSOP package and 56-pin TSSOP package

Benefits
* Supports next-generation Pentium® processors using differential clock drivers
* Motherboard clock generator
- Supports multiple CPUs and a chipset
- Support for PCI slots and chipset
- Supports AGP, DRCG reference, and Hub Link
- Supports USB host controller and graphic controller
- Supports ISA slots and I/O chip
* Enables reduction of electromagnetic interference (EMI) and overall system cost
* Enables ACPI-compliant designs
* Supports up to four CPU clock frequencies
* Enables ATE and “bed of nails” testing
* Widely available standard package enables lower cost

W320-04H
W320-04HT
W320-04X
W320-04XT
 

W320-04 - 200-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs

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