Features
* Compliant with Intel® CK-Titan clock synthesizer/driver specifications
* Multiple output clocks at different frequencies
- Three pairs of differential CPU outputs, up to 200 MHz
- Ten synchronous PCI clocks, three free-running
- Six 3V66 clocks
- Two 48-MHz clocks
- One reference clock at 14.318 MHz
- One VCH clock
* Spread Spectrum clocking (down spread)
* Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#)
* Three Select inputs (Mode select and IC Frequency Select)
* OE and Test Mode support
* 56-pin SSOP package and 56-pin TSSOP package

Benefits
* Supports next-generation Pentium® processors using differential clock drivers
* Motherboard clock generator
- Supports multiple CPUs and a chipset
- Support for PCI slots and chipset
- Supports AGP, DRCG reference, and Hub Link
- Supports USB host controller and graphic controller
- Supports ISA slots and I/O chip
* Enables reduction of electromagnetic interference (EMI) and overall system cost
* Enables ACPI-compliant designs
* Supports up to four CPU clock frequencies
* Enables ATE and “bed of nails” testing
* Widely available standard package enables lower cost

W320-04H
W320-04HT
W320-04X
W320-04XT

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Functional Description
 The Cypress PALCE22V10 is a CMOS Flash Erasable second-generation programmable array logic device.
It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs.
The PALCE22V10 can be electrically erased and reprogrammed.
The programmable macrocell provides the capability of defining the architecture of each output individually.
Each of the 10 potential outputs may be specified as “registered” or “combinatorial.”
Polarity of each output may also be individually selected, allowing complete flexibility of output configuration.
Further configurability is provided through “array” configurable “output enable” for each potential output.
This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output.
By providing this variable structure, the PALCE 22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance.
Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions.
The device automatically resets upon power-up.
The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity.
Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible.
The 10 potential outputs are enabled using product terms.
Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output.
Each of these outputs is achieved through an individual programmable macrocell.
These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output.
In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array.
This information is available for establishing the next result in applications such as control state machines.
In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array.
The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic.
Along with this increase in functional density, the Cypress PALCE22V10 provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability.

Features
* Low power
- 90 mA max. commercial (10 ns)
- 130 mA max. commercial (5 ns)
* CMOS Flash EPROM technology for electrical erasability and reprogrammability
* Variable product terms
- 2 x(8 through 16) product terms
* User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
* Up to 22 input terms and 10 outputs
* DIP, LCC, and PLCC available
- 5 ns commercial version
- 4 ns tCO
- 3 ns tS
- 5 ns tPD
- 181-MHz state machine
- 10 ns military and industrial versions
- 7 ns tCO
- 6 ns tS
- 10 ns tPD
- 110-MHz state machine
- 15-ns commercial, industrial, and military versions
- 25-ns commercial, industrial, and military versions
* High reliability
- Proven Flash EPROM technology
- 100% programming and functional testing

PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25

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Features
• Fast clock speed: 200, 167, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0, 3.4, 3.8, and 4.2 ns
• Optimal for depth expansion
• 3.3V (–5% / +10%) power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down available using ZZ mode or CE deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version

Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single- layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.
The CY7C1380B and CY7C1382B SRAMs integrate 524,288x36 and 1,048,576x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQa,b,c,d and DPa,b,c,d apply to CY7C1380B and DQa,b and DPa,b apply to CY7C1382B. a, b,
c, d each are 8 bits wide in the case of DQ and 1 bit wide in the case of DP.
Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally
generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPc. BWd controls DQd and DPd. BWa, BWb,
BWc, and BWd can be active only with BWE being LOW. GW
being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates
pipelined enable circuit for easy depth expansion without penalizing system performance.
All inputs and outputs of the CY7C1380B and the CY7C1382B are JEDEC standard JESD8-5 compatible.
TAG SRAM

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Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-tSA = 45 ns
-tCO = 15 ns
• Low power
-120 mA
• On-chip, edge-triggered output registers
• Programmable synchronous or asynchronous output enable
• EPROM technology, 100% programmable
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Slim 300-mil package
• Capable of withstanding >2001V static discharge

Functional Description
The CY7C287 is a high-performance 64K x 8 CMOS PROM.
The CY7C287 is equipped with an output register and an output output enable that can be programmed to be synchronous (ES) or asynchronous (E). It is available in a 28-pin, 300-mil package.
The address set-up time is 45 ns and the time from clock HIGH to output valid is 15 ns.
The CY7C287 is available in a cerDIP package equipped with an erasure window to provide reprogrammability. When exposed to UV light, the PROM is erased and can be reprogrammed.
The memory cells utilize proven EPROM floating- gate technology and byte-wide intelligent programming algorithms.
The CY7C287 offers the advantage of low power, superior performance, and programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements
allow for gang programming. The EPROM cells allow for each memory location to be 100% tested with each cell being programmed, erased, and repeatedly exercised prior to encapsulation.
Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming.
Reading the CY7C287 is accomplished by placing an active LOW signal on E/ES. The contents of the memory location addressed by the address lines (A0 - A15) will become available on the output lines (O0 - O7) on the next rising of CP.

CY7C287-45JC
CY7C287-45PC
CY7C287-45WC

TAG Register

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Features
• 4.5V-5.5V operation
• CMOS for optimum speed/power
• Low active power
-660 mW (max.)
• Low standby power (L version)
-2.75 mW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options

Functional Description
The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 99% when deselected.
Writing to the device is accomplished by taking chip enable one (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip enable one (CE) and output enable (OE) LOW while forcing write enable (WE). Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 450-mil-wide body width SOIC package.

CY62148-55SC
CY62148L-55SC
CY62148-70SC
CY62148L-70SC
CY62148-70SI
CY62148L-70SI

TAG RAM, Static

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Features
* All output pair skew <100 ps typical (250 max)
* 3.75 to 100 MHz output operation
* User selectable output functions
+ Selectable skew to 18 ns
+ Inverted and non-inverted
+ Operation at ½ and ¼ input frequency
+ Operation at 2x and 4x input frequency (input as low as 3.75 MHz)
* Zero input to output delay
* 50% duty cycle outputs
* Outputs drive 50Ω terminated lines
* Low operating current
* 32-pin PLCC/LCC package
* Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Functional Description
The CY7B9911 High Speed Programmable Skew Clock Buffer (PSCB) offers user selectable control over system clock functions. This multiple output clock driver provides the system
integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual TTL drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They deliver minimal and specified output skews and full swing logic levels.
Each output is hardwired to one of nine delay or function configurations.
Delay increments of 0.6 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that is multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty enabling maximum system clock speed and flexibility.


CY7B9911–5JC
CY7B9911–5JCT
CY7B9911–7JC

TAG Buffer, Clock

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Features
• High speed
—tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
—1320 mW (max.)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bits
• Available in 44-pin TSOP II and 400-mil SOJ

Functional Description
The CY7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15).
 
 Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes.

 The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021 is available in standard 44-pin T Type II and 400-mil-wide SOJ packages

CY7C1021-10VC
CY7C1021-10ZC
CY7C1021L-10ZC
CY7C1021-12VC
CY7C1021-12VI
CY7C1021-12ZC
CY7C1021-15VC
CY7C1021-15VI
CY7C1021-15ZC
CY7C1021-15ZI
CY7C1021L-15ZC
CY7C1021-20VC
CY7C1021-20ZCSOP
TAG RAM, Static

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