FUNCTIONAL DESCRIPTION
The 3D7323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched, independent delay lines. Delay values can range from 6ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D7323 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7323 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Delay range: 6 through 6000ns
*Delay tolerance: 2% or 1.0ns
*Temperature stability: ±3% typ (-40C to 85C)
*Vdd stability: ±1% typical (4.75V to 5.25V)
* Minimum input pulse width: 20% of total delay
*14-pin DIP available as drop-in replacement for hybrid delay lines  

3D7323 - MONOLITHIC TRIPLE FIXED DELAY LINE

DESCRIPTION
The 3D3701 Delay Line Oscillator product family consists of fixed-frequency CMOS integrated circuit oscillators. Each package contains a single oscillator, which is gated and can therefore be synchronized to an external signal. The device frequency can range from 0.3MHz through 100MHz. The 3D3701 has two outputs that are in phase when the oscillator is running. The 3D3701 is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC package.

FEATURES
*All-silicon, low-power CMOS technology
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Frequency range: 0.3MHz through 100MHz
*Frequency tolerance: 0.5% typical
*Temperature stability: ±1.5% typical (-40C to 85C)
*Vdd stability: ±0.5% typical (3.0V to 3.6V)
*14-pin DIP available as drop-in replacements for hybrid delay line oscillators

 

3D3701 - MONOLITHIC GATED DELAY LINE OSCILLATOR

FUNCTIONAL DESCRIPTION
The DDU39F-series device is a mechanically variable, FAST-TTL interfaced delay line.
The signal input (IN) is reproduced at the tap output (OUT), shifted by an amount which can be adjusted between 7ns and 25ns.
The device operates from a single 5V supply and is TTL interfaced, capable of driving up to 10 TTL loads.

FEATURES
*Ideal for “Set and Forget” applications
*Multi-turn adjustment screw (approx. 15 turns)
*Fits standard 16-pin DIP socket
*Input & output fully TTL interfaced & buffered (10 T2L fan-out capability)
*Resolution: 0.5ns typical
*Adjustment range: 7ns to 25ns
*Output rise time: 4ns typical
*Min. input pulse width: 10ns
*Power dissipation: 230mW maximum
*Operating temperature: 0° to 70°C (Commercial) -55° to 125°C (Military)

APPLICATION NOTES
*HIGH FREQUENCY RESPONSE
The DDU39F tolerances are guaranteed for input pulse widths and periods greater than those
specified in the test conditions.
Although the device will function properly for pulse widths as small as 10ns and periods as small 20ns (for a symmetric input), the delays may deviate from their values at low frequency.
However, for a given input condition, the deviation will be repeatable from pulse to pulse.
Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.
*POWER SUPPLY BYPASSING
The DDU39F relies on a stable power supply to produce repeatable delays within the stated
tolerances.
A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended.
A wide VCC trace and a clean ground plane should be used.

DDU39F
DDU39FM  

DDU39F-MECHANICALLY VARIABLE TTL DELAY LINE

FUNCTIONAL DESCRIPTION
The 3D7521 is a monolithic CMOS Manchester Encoder.
The clock and data, present at the unit input, are combined into a single bi-phase-level signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition.
The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ).
All pins marked N/C must be left unconnected.
The all-CMOS 3D7521 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Encoder.
It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads.
It is offered in space saving surface mount 8-pin and 14-pin SOICs.
The 3D7521 Manchester Encoder samples the data input at the rising edge of the input clock.
The sampled data is used in conjunction with the clock rising and falling edges to generate the by-phase level Manchester code.

FEATURES
* All-silicon, low-power CMOS technology
* TTL/CMOS compatible inputs and outputs
* Vapor phase, IR and wave solderable
* Low ground bounce noise
* Maximum data rate: 50 MBaud  

3D7521 - MONOLITHIC MANCHESTER ENCODER(SERIES 3D7521)

FUNCTIONAL DESCRIPTION
 The 3D7522 product family consists of monolithic CMOS Manchester Decoders.
The unit accepts at the RX input a bi-phase-level, embedded-clock signal.
In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition.
The recovered clock and data signals are presented on CLK and DATB, respectively, with the data signal inverted.
The operating baud rate (in MBaud) is specified by the dash number.
The input baud rate may vary by as much as ±15% from the nominal device baud rate without compromising the integrity of the information received.
Because the 3D7522 is not PLL-based, it does not require a long preamble in order to lock onto the received signal.
Rather, the device requires at most one bit cell before the data presented at the output is valid.
This is extremely useful in cases where the information arrives in bursts and the input is otherwise turned off.
The all-CMOS 3D7522 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Decoders.
It is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads.
It is offered in space saving surface mount 8-pin and 14-pin SOICs.

FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Low ground bounce noise
• Maximum data rate: 50 MBaud
• Data rate range: ±15%
• Lock-in time: 1 bit

3D7522-0.5
3D7522-1
3D7522-5
3D7522-10
3D7522-20
3D7522-25
3D7522-50  

3D7522 - MONOLITHIC MANCHESTER DECODER