CS101 - CMOS Standard Cell
Fujitsu 2008/11/20 09:28
DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use. As well as providing a maximum of 91 million gates, approximately twice the level of integration achieved in previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
*Technology :
- 90 nm Si gate CMOS
- 6- to 10-metal layers.
- Low-K (low permittivity) material is used for all dielectric inter-layers.
- Three different types of core transistors (low leak, standard, and high speed) can be used on the same chip.
- The design rules comply with industry standard processes.
*Power supply voltage : + 0.9 V to + 1.3 V (A wide range is supported.)
*Operation junction temperature : − 40 °C to + 125 °C (standard)
*Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
*Gate power consumption : 2.7 nW/gate (1.2 V, 2 NAND, F/O = 1, operating rate 0.5) , 1.8 nW/gate (1.0 V, 2 NAND, F/O = 1, operating rate 0.5)
*High level of integration : Up to 91 million gates
*Reduced chip sized realized by I/O with pad.
*Two types of library sets are supported. (Performance focused (1.2 V) , Low power consumption supported (0.9 V to 1.3 V) )
*Low power consumption design (multi-power supply design and power gating) is supported.
*Compliance with industry standard design rules enables non-Fujitsu Microelectronics commercial macros to be easily incorporated.
*Compiled cell (RAM, ROM, others)
*Support for ultra high speed (up to 10 Gbps) interface macros.
*Special interfaces (LVDS, SSTL2, others)
*Supports use of industry standard libraries (.LIB).
*Uses industry standard tools and supports the optimum tools for the application.
*Short-term development using a physical prototyping tool
*One pass design using a physical synthesis tool
*Hierarchical design environment for supporting large-scale circuits
*Support for Signal Integrity, EMI noise reduction
*Support for static timing sign-off
*Optimum package range : FBGA, FC-BGA, PBGA,TEBGA
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use. As well as providing a maximum of 91 million gates, approximately twice the level of integration achieved in previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.
FEATURES
*Technology :
- 90 nm Si gate CMOS
- 6- to 10-metal layers.
- Low-K (low permittivity) material is used for all dielectric inter-layers.
- Three different types of core transistors (low leak, standard, and high speed) can be used on the same chip.
- The design rules comply with industry standard processes.
*Power supply voltage : + 0.9 V to + 1.3 V (A wide range is supported.)
*Operation junction temperature : − 40 °C to + 125 °C (standard)
*Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
*Gate power consumption : 2.7 nW/gate (1.2 V, 2 NAND, F/O = 1, operating rate 0.5) , 1.8 nW/gate (1.0 V, 2 NAND, F/O = 1, operating rate 0.5)
*High level of integration : Up to 91 million gates
*Reduced chip sized realized by I/O with pad.
*Two types of library sets are supported. (Performance focused (1.2 V) , Low power consumption supported (0.9 V to 1.3 V) )
*Low power consumption design (multi-power supply design and power gating) is supported.
*Compliance with industry standard design rules enables non-Fujitsu Microelectronics commercial macros to be easily incorporated.
*Compiled cell (RAM, ROM, others)
*Support for ultra high speed (up to 10 Gbps) interface macros.
*Special interfaces (LVDS, SSTL2, others)
*Supports use of industry standard libraries (.LIB).
*Uses industry standard tools and supports the optimum tools for the application.
*Short-term development using a physical prototyping tool
*One pass design using a physical synthesis tool
*Hierarchical design environment for supporting large-scale circuits
*Support for Signal Integrity, EMI noise reduction
*Support for static timing sign-off
*Optimum package range : FBGA, FC-BGA, PBGA,TEBGA
CS101 - CMOS Standard Cell
