GENERAL DESCRIPTION
The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability.

FEATURES
*8 Differential LVDS outputs
*CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Maximum output frequency: 700MHz
*Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
*Translates any single-ended input signal to LVDS with resistor bias on nCLK input
*Multiple output enable inputs for disabling unused outputs in reduced fanout applications
*Output skew: 50ps (maximum)
*Part-to-part skew: 550ps (maximum)
*Propagation delay: 2.4ns (maximum)
*3.3V operating supply
*0°C to 70°C ambient operating temperature
*Lead-Free package RoHS compliant

ICS85408BG, ICS85408BGT
ICS85408BGLF, ICS85408BGLFT  

ICS85408 - LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

GENERAL DESCRIPTION
The ICS858012 is a high speed 1-to-2 Differentialto-2.5V, 3.3V LVPECL Fanout Buffer and is a member of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS858012 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, LVHSTL and HCSL to be easily interfaced to the input with minimal use of external components. The ICS858012 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in 8space-constrained applications

FEATURES
*Two differential LVPECL outputs
*One differential LVPECL clock input
*IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Output frequency: 2GHz (typical)
*Output skew: <15ps (typical)
*Part-to-part skew: TBD
*Additive phase jitter, RMS: TBD
*Propagation delay: 350ps (typical)
*Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V
*-40°C to 85°C ambient operating temperature
*Availabe in both standard and lead-free RoHS compliant packages

ICS858012AK, ICS858012AKT, ICS858012AKLF, ICS858012AKLFT  

ICS858012 - LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER

General Description
The AV9155C-44 is a low cost frequency generator designed specifically for desktop and  notebook PC applications with either 3.3V or 5.0V power supply voltage.
Its CPU clocks provide all necessary CPU frequencies for 286, 386 and 486 systems, including support for the latest speeds of processors.
The device uses a 14.318 MHz crystal to generate the CPU and all peripheral clocks for integrated desktop motherboards.
The dual 14.318 MHz clock outputs allows one output for the system and one to be the input to an ICS graphics frequency generator such as the AV9194.
The CPU clock offers the unique feature of smooth, glitchfree transitions from one frequency to the next, making this ideal device to use whenever slowing the CPU speed.
The AV9155C-44 makes a gradual transition between frequencies, so that it obeys the Intel cycle-to-cycle timing specification for 486 systems.
The simultaneous 2X and 1X CPU clocks offer controlled skew to within 1.5ns (max) of each other.

Features
*Compatible with 286, 386, and 486 CPUs
*Supports turbo modes
*Generates communications clock, keyboard clock, floppy disk clock, system reference clock, bus clock and CPU clock
*Output enable tristates outputs
*Up to 100 MHz at 5V or 3.3V
*20-pin DIP or SOIC
*All loop filter components internal
*Skew-controlled 2X and 1X CPU clocks
*Power-down option

AV9155C-44CW20  

AV9155C-44 - Low Cost 20-Pin Frequency Generator

GENERAL DESCRIPTION
The ICS87993I is a PLL clock driver designed specifically for redundant clock tree designs.
The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signal frequency and phase while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer performance.
The ICS87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H).
If that CLK is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated.

FEATURES
* 5 differential 3.3V LVPECL outputs
* Selectable differential clock inputs
* CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
* VCO range: 200MHz to 500MHz
* External feedback for “zero delay” clock regeneration with configurable frequencies
* Cycle-to-cycle jitter (RMS): 20ps (maximum)
* Output skew: 70ps (maximum), within one bank
* 3.3V supply voltage
* -40°C to 85°C ambient operating temperature
* Pin compatible with MPC993

ICS87993AYI
ICS87993AYIT  

ICS87993I - 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

General Description
The ICS932S422C is a main clock synthesizer for CK410-generation Intel server platforms.
The ICS932S422C is driven with a 14.318MHz crystal. It generates 5 CPU output pairs up to 400MHz and PCI-Express clocks at 100 or 200 MHz.
The 48 MHz USB clock is an exact 48.000 MHz clock.

Features/Benefits
* Supports spread spectrum modulation, 0 to -0.5% down spread
* Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error
* CPU clocks independent of SRC/PCI clocks
* D2/D3 SMBus address
* Compliant with PCIe Gen II phase noise specifications

Output Features
* 5 - 0.7V current-mode differential CPU pairs
* 4 - 0.7V current-mode differential SRC pair
* 4 - PCI (33MHz)
* 3 - PCICLK_F, (33MHz) free-running
* 1 - 48MHz
* 2 - REF, 14.318MHz

 

ICS932S422C - PCIe Gen 2 main Clock for Intel-based Servers