Product Highlights
* Non-Transparent PCI-to-PCI bridge technology for high-performance embedded and intelligent I/O applications
* Independent address spaces and asynchronous clocks deliver unparalleled application
flexibility
* 64-bit primary and secondary bus interfaces deliver high performance for data-intensive applications
* Compliant with ACPI and PCI bus power management specifications
* Secondary bus arbitration support for up to nine bus master devices
* Evaluation Design Kit speeds time-to-market
* Fully compliant with Revision 2.3 of the PCI specification including delayed transactions
* Available in 33 and 66 MHz

Product Overview
Intel’s 21555 Non-Transparent PCI-to-PCI bridge chip enables add-in card vendors to deliver high-performance, intelligent option cards and embedded products that previously were not possible. Designed specifically for applications where a processor is used behind a PCI-to-PCI bridge, the 21555 provides a clean architecture for creating a product with multiple processor domains.

Efficient Management of System and Subsystem Resources
The 21555 provides independent primary and secondary address spaces, which allow independent host and local address mapping.
With this key feature, local memory requirements need not impact the host address map. The 21555 performs address translation between the primary and secondary buses, resolving address resource conflicts between the host and local address domains.

 Featuring a subsystem PCI configuration boundary, the 21555 allows the local processor to
have complete PCI configuration control of subsystem devices, without host interference. This
advanced feature also allows the 21555 to present subsystem, such as a RAID controller, as a
single virtual PCI device. An added benefit of this design is the ability to easily identify a single
device driver for the entire subsystem. Another feature of the 21555, a serial ROM interface,
allows manufacturers to customize the 21555 for particular application by pre-loading the ROM
with vendor-specific configuration data.

A Unique Bridge Architecture
Intel’s 21555 is a unique new Non-Transparent PCI-to-PCI bridge solution. The 21555 provides
designers of intelligent controllers and embedded systems with a Non-Transparent PCI to- PCI bridge solution capable of resolving resource conflicts between a PCI-based host system and a PCI-based subsystem. This gives a local processor maximum flexibility in mapping and managing subsystem resources.

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The Intel® LXT9785 and Intel® LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone.

Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX) Ethernet over fiber-optic media.

The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices
support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a
single 2.5 V power supply.

Applications
* Enterprise switches
* IP telephony switches
* Storage Area Networks
* Multi-port Network Interface Cards (NICs)

Product Features
* Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters.
* 100BASE-FX fiber-optic capability on all ports.
* 2.5 V operation.
* Low power consumption; 250 mW per port typical.
* Multiple RMII or SMII/SS-SMII ports for independent PHY port operation.
* Auto MDI/MDIX crossover capability.
* Proprietary Optimal Signal Processing™ architecture improves SNR by 3 dB over ideal analog filters.
* Optimized for dual-high stacked RJ-45 applications.
* MDIO sectionalization into 2x4 or 1x8 configurations.
* Supports both auto-negotiation systems and legacy systems without auto-negotiation
capability.
* Robust baseline wander correction.
* Configurable through the MDIO port or external control pins.
* JTAG boundary scan.
* 208-pin PQFP: LXT9785HC, LXT9785EHC, LXT9785HE.
* 241-ball BGA: LXT9785BC, LXT9785EBC.
* 196-ball BGA: LXT9785MBC
* DTE detection for remote powering applications (LXT9785E only).
* Extended temperature operation of -40oC to +85oC (LXT9785HE).

LXT9785HC, LXT9785EHC, LXT9785HE, LXT9785E

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ㅁ Flash Electrical Chip-Erase
-1 Second Typical Chip-Erase
ㅁ Quick Pulse Programming Algorithm
-10 ms Typical Byte-Program
-2 Second Chip-Program
ㅁ 100,000 Erase/Program Cycles
ㅁ 12.0V g5% VPP
ㅁ High-Performance Read -65 ns Maximum Access Time
ㅁ CMOS Low Power Consumption
-10 mA Typical Active Current
-50 mA Typical Standby Current
-0 Watts Data Retention Power
ㅁ Integrated Program/Erase Stop Timer
ㅁ Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface
ㅁ Noise Immunity Features
-g10% VCC Tolerance
-Maximum Latch-Up Immunity through EPI Processing
ㅁ ETOXTM Nonvolatile Flash Technology
-EPROM-Compatible Process Base
-High-Volume Manufacturing Experience
ㅁ JEDEC-Standard Pinouts
-32-Pin Plastic Dip
-32-Lead PLCC
-32-Lead TSOP
(See Packaging Spec., Order Ý231369)
ㅁ Extended Temperature Options
TAG CMOS

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