DESCRIPTION
The QS5805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of five non-inverting outputs. The QS5805 device provides low propagation delay buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.
The QS5805 is characterized for operation at -40°C to +85°C.

FEATURES
*10 CMOS outputs
*Monitor output
*Rail-to-rail output voltage swing
*Input hysteresis for better noise margin
*Guaranteed low skew:
- 0.7ns output skew (same bank)
- 0.8ns output skew (different banks)
- 1.2ns part-to-part skew
*Std., A, and B speed grades
*Available in QSOP and SOIC packages

QS5805A, QS5805B  

QS5805 - GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER

DESCRIPTION
The IDT29FCT520A/B/C contains four 8-bit positive edgetriggered registers.
These may be operated as a dual 2-level or as a single 4-level pipeline.
A single 8-bit input is provided and any of the four registers is available at the 8-bit, 3-state
output.
In the IDT29FCT520A/B/C when data is entered into the first level (I = 2 or I = 1), the existing data in the first level is moved to the second level.
Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0).
This transfer also causes the first level to change.

FEATURES
*Equivalent to AMD’s Am29520 bipolar Multilevel Pipeline Register in pinout/function, speed and output drive over full temperature and voltage supply extremes
*Four 8-bit high-speed registers
*Dual two-level or single four-level push-only stack operation
*All registers available at multiplexed output
*Hold, transfer and load instructions
*Provides temporary address or data storage
*IOL = 48mA (commercial), 32mA (military)
*CMOS power levels (1mW typ. static)
*Substantially lower input current levels than AMD’s bipolar (5mA typ.)
*TTL input and output level compatible
*CMOS output level compatible
*Manufactured using advanced CMOS processing
*Available in 300 mil plastic and hermetic DIP, as well as LCC, SOIC and CERPACK
*Product available in Radiation Tolerant and Radiation Enhanced versions
*Military product compliant to MIL-STD-883, Class B

IDT29FCT520B
IDT29FCT520C
 

IDT29FCT520A-MULTILEVEL PIPELINE REGISTER

Description
The ICS251 is a low cost, single-output, field programmable clock synthesizer.
The ICS251 can generate an output frequency from 314 kHz to 200 MHz and may employ
Spread Spectrum techniques to reduce system electro-magnetic interference (EMI).
Using ICS’ VersaClock™ software to configure the PLL and output, the ICS251 contains a One-Time Programmable (OTP) ROM to allow field programmability.
Programming features include 4 selectable configuration registers.
The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock.
It can replace multiple crystals and oscillators, saving board space and cost.
The device also has a power-down feature that tri-states the clock outputs and turns off the PLLs when the PDTS pin is taken low.
The ICS251 is also available in factory programmed custom versions for high-volume applications.

Features
* 8-pin SOIC package
* Four addressable registers
* Input crystal frequency of 5 to 27 MHz
* Clock input frequency of 3 to 150 MHz
* Output clock frequencies up to 200 MHz
* Configurable Spread Spectrum Modulation
* Operating voltage of 3.3 V
* Replaces multiple crystals and oscillators
* Controllable output drive levels
* Advanced, low-power CMOS process
* Available in RoHS compliant packagingFeatures
* 8-pin SOIC package
* Four addressable registers
* Input crystal frequency of 5 to 27 MHz
* Clock input frequency of 3 to 150 MHz
* Output clock frequencies up to 200 MHz
* Configurable Spread Spectrum Modulation
* Operating voltage of 3.3 V
* Replaces multiple crystals and oscillators
* Controllable output drive levels
* Advanced, low-power CMOS process
* Available in RoHS compliant packaging

ICS251PM
ICS251PMI
ICS251PMLF
ICS251PMILF  

ICS251 - FIELD PROGRAMMABLE SS VERSACLOCK SYNTHESIZER

General Description
The ICS950910 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with PC133 or DDR memory.
The ICS950910 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub).
This part incorporates ICS's newest clock technology which offers more robust features and functionality.
Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock.
M/N control can configure output frequency with resolution up to 0.1MHz increment.

Features/Benefits
* Programmable output frequency.
* Programmable output divider ratios.
* Programmable output rise/fall time.
* Programmable output skew.
* Programmable spread percentage for EMI control.
* DDR output buffer supports up to 200MHz.
* Watchdog timer technology to reset system if system malfunctions.
* Programmable watch dog safe frequency.
* Support I2C Index read/write and block read/write operations.
* Uses external 14.318MHz crystal.  

ICS950910 - Programmable Timing Control Hub™ for P4™

DESCRIPTION
 This 1-bit to 4-bit address driver is built using advanced dual metal CMOS technology.
The ALVCH162344 device is used in applications in which four separate memory locations must be addressed by a single address.
The ALVCH162344 has series resistors in the device output structure which will significantly reduce line noise when used with light loads.
This driver has been designed to drive ±12mA at the designated threshold levels.
The ALVCH162344 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high-impedance.
This prevents floating inputs and eliminates the need for pull-up/down resistors.

FEATURES
* 0.5 MICRON CMOS Technology
* Typical tSK(o) (Output Skew) < 250ps
* ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
* VCC = 3.3V ± 0.3V, Normal Range
* VCC = 2.7V to 3.6V, Extended Range
* VCC = 2.5V ± 0.2V
* CMOS power levels (0.4μ W typ. static)
* Rail-to-Rail output swing for increased noise margin
* Available in SSOP, TSSOP, and TVSOP packages

APPLICATIONS
* 3.3V high speed systems
* 3.3V and lower voltage computing systems

DRIVE FEATURES
* Balanced Output Drivers: ±12mA
* Low switching noise

IDT74ALVCH162344PV
IDT74ALVCH162344PA
IDT74ALVCH162344PF

 

IDT74ALVCH162344 - 3.3V CMOS 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD