Description
The M45PE16 is a 16Mbit (2M x 8 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or
Page Program instruction. The Page Write instruction consists of an integrated Page Erase
cycle followed by a Page Program cycle.
The memory is organized as 32 sectors, each containing 256 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or
2,097,152 Bytes.
The memory can be erased a page at a time, using the Page Erase instruction, or a sector
at a time, using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M45PE16 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.

Features
*SPI bus compatible serial interface
*50 MHz clock rate (maximum)
*16 Mbit of Page-Erasable Flash memory
*Page of 256 Bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
*Sector Erase (512 Kbit)
*Hardware Write protection of the bottom sector (64 KBytes)
*Electronic Signature
– JEDEC Standard two-Byte signature (4015h)
*2.7 to 3.6 V single supply voltage
*Deep Power-down mode 1 μA (typical)
*More than 100 000 Write cycles
*More than 20 years’ data retention
*Packages
– ECOPACK® (RoHS compliant)

M45PE16-VMW6TP, M45PE16-VMP6TP, M45PE16-VMW6P, M45PE16-VMP6P, M45PE16-VMW6TG, M45PE16-VMP6TG, M45PE16-VMW6G, M45PE16-VMP6G  

M45PE16 - 16 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability and a 50 MHz SPI bus interface

Description
The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) serial paged Flash memories, respectively.
They are accessed by a high speed SPI-compatible bus.
The memories can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction.
The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages.
Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131, 072 bytes.
The memories can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase instruction.
The memory can be write protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on the application needs.
The protection granularity is of 64 Kbytes (sector granularity).

Features
* 1 or 2 Mbit of page-erasable Flash memory
* 2.7 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 75 MHz clock rate (maximum)
* Page size: 256 bytes
- Page Write in 11 ms (typical)
- Page Program in 0.8 ms (typical)
- Page Erase in 10 ms (typical)
* SubSector Erase (32 Kbits)
* Sector Erase (512 Kbits)
* Bulk Erase (1 Mbit for M25PE10, 2 Mbits for M25PE20)
* Deep Power-down mode 1 μA (typical)
* Electronic signature
- JEDEC standard two-byte signature
(8012h for M25PE20, 8011h for M25PE10)
- Unique ID code (UID) with 16 bytes readonly, available upon customer request only in the T9HX process
* Software write protection on a 64-Kbyte sector basis
* More than 100 000 Write cycles
* More than 20 years data retention
* Hardware write protection of the memory area selected using the BP0 and BP1 bits
* Package
- ECOPACK® (RoHS compliant)

M25PE10
M25PE20-VMN6TP
M25PE20-VMP6TP

 

M25PE20 - 1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout

Description
The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the page program instruction.
The memory is organized as 2 sectors, each containing 128 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.
The whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction.

Features
* 512 Kbits of flash memory
* Page program (up to 256 bytes) in 1.4 ms (typical)
* Sector erase (256 Kbits) in 0.65 s (typical)
* Bulk erase (512 Kbits) in 0.85 s (typical)
* 2.3 to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 50 MHz clock rate (maximum)
* Deep power-down mode 1 μA (typical)
* Electronic signatures
- JEDEC standard two-byte signature (2010h)
- RES instruction, one-byte, signature (05h), for backward compatibility
* More than 100,000 erase/program cycles per sector
* More than 20 years data retention
* ECOPACK® packages available  

M25P05-A - 512-Kbit, serial flash memory, 50 MHz SPI bus interface

Description
 The NAND04G-B2D and NAND08G-BxC are part of the NAND Flash 2112 byte/1056 word page family of non-volatile Flash memories.
They use NAND cell technology have a density of 4 Gbits and 8 Gbits, respectively.
The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each.
This multiplane architecture makes it possible to program 2 pages at a time (one in each plane),
or to erase 2 blocks at a time (one in each plane).
This feature reduces the average program and erase times by 50%.
The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of which feature a multiplane architecture.
In the NAND08G-B2C devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time.
In the NAND08G-B4C devices, each NAND04G-B2D die can be accessed independently using two sets of signals.
The devices operate from a 1.8 V or 3 V voltage supply.
Depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare) or or 1056 words (1024 + 32 spare), respectively.
The address lines are multiplexed with the data input/output signals on a multiplexed x8
input/output bus.
This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 100 000 cycles with ECC (error correction
code) on.
To extend the lifetime of NAND Flash devices, the implementation of an ECC is strongly recommended.
A Write Protect pin is available to provide hardware protection against program and erase
operations.
The devices feature an open-drain ready/busy output that identifies if the P/E/R (program/erase/read) Controller is currently active.
The use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor.
A Copy Back Program command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
An embedded error detection code is automatically executed after each copy back operation: 1 error bit can be detected for every 528 bits.
With this feature it is no longer necessary, nor recommended, to use an external 2- bit ECC to detect copy back operation errors.
The devices have a cache read feature that improves the read throughput for large files.
During cache reading, the device loads the data in a Cache Register while the previous data is transferred to the I/O buffers to be read.
The devices have the Chip Enable ‘don’t care’ feature, which allows code to be directly downloaded by a microcontroller.
This is possible because Chip Enable transitions during the latency time do not stop the read operation.
Both the NAND04G-B2D and NAND08G-BxC support the ONFI 1.0 specification.

Features
* High density NAND Flash Memory
- Up to 8 Gbit memory array
- Cost-effective solution for mass storage applications
* NAND interface
- x8 or 16x bus width
- Multiplexed address/data
* Supply voltage: 1.8 V or 3.0 V device
* Page size
- x8 device: (2048 + 64 spare) bytes
- x16 device: (1024 + 32 spare) words
* Block size
- x8 device: (128K + 4 K spare) bytes
- x16 device: (64K + 2 K spare) words
* Multiplane architecture
- Array split into two independent planes
- Program/erase operations can be performed on both planes at the same time
* Page read/program
- Random access: 25 μs (max)
- Sequential access: 25 ns (min)
- Page program time: 200 μs (typ)
- Multiplane page program time (2 pages): 200 μs (typ)
* Copy back program with automatic error detection code (EDC)
* Cache read mode
* Fast block erase
- Block erase time: 1.5 ms (typ)
- Multiblock erase time (2 blocks): 1.5 ms (typ)
* Status Register
* Electronic signature
* Chip Enable ‘don’t care’
* Serial number option
* Data protection:
- Hardware program/erase disabled during power transitions
- Non-volatile protection option
* ONFI 1.0 compliant command set
* Data integrity
- 100 000 program/erase cycles (with ECC (error correction code))
- 10 years data retention
* ECOPACK® packages

NAND04GW4B2D
NAND08GR3B2C
NAND08GW3B2C
NAND08G-BXC
NAND04GR3B2D

 

NAND04G-B2D - 4 Gbit, 8 Gbit, 2112 byte/1056 word page multiplane architecture, 1.8 V or 3 V, NAND Flash memories

Description
 The M25P40 is a 4 Mbit (512 K × 8) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 8 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M25P40 in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant.

Features
* 4 Mbit of Flash memory
* 2.3 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 50 MHz clock rate (maximum)
* Page Program (up to 256 bytes) in 1.5 ms (typical)
* Sector Erase (512 Kbit) in 1 s (typical)
* Bulk Erase (4 Mbit) in 4.5 s (typical)
* Deep Power-down mode 1 μA (typical)
* Hardware Write Protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2)
* Electronic signatures
– JEDEC standard two-byte signature (2013h)
– RES instruction, one-byte, signature (12h), for backward compatibility
* Packages
– ECOPACK® (RoHS compliant)

M25P40-VMN6TP/X
M25P40-VMP3G/X

 

M25P40 - 4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface