General Description
The S70GL01GN00 is a 1024 Mbit, single power supply flash memory device organized as two S29GL512N dies in a single 64-ball Fortified-BGA package. Each S29GL512N die is 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 110 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide‚ on page 5 and the Ordering Information‚ on page 9. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE# or CE2#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

Software & Hardware Features
*Software features
- Program Suspend and Resume: read other sectors before programming operation is completed
- Erase Suspend and Resume: read/program other sectors before an erase operation is completed
- Data# polling and toggle bits provide status
- Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
*Hardware features
- Advanced Sector Protection
- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
- Hardware reset input (RESET#) resets device
- Ready/Busy# output (RY/BY#) detects program or erase cycle completion

S70GL01GN00FAI010, S70GL01GN00FFI010, S70GL01GN00FAI020 S70GL01GN00FFI020, S70GL01GN00FAI120, S70GL01GN00FFI120 S70GL01GN00FAI012, S70GL01GN00FFI012, S70GL01GN00FAI022
S70GL01GN00FFI022, S70GL01GN00FAI122, S70GL01GN00FFI122
S70GL01GN00FAI013, S70GL01GN00FFI013, S70GL01GN00FAI023 S70GL01GN00FFI023, S70GL01GN00FAI123, S70GL01GN00FFI123  

S70GL01GN00 - 1024 Megabit, 3.0 Volt-only Page Mode Flash Memory Featuring 110 nm MirrorBit™ Process Technology

DESCRIPTION
The MBM29LV320TE/BE is 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M words of 16 bits each. The device is offered in a 48-pin TSOP (1) and 63-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard device offers access times 80 ns, 90 ns and 100 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention the device has separate chip enable(CE), write enable(WE) and output enable (OE) controls.
The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This invokes the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This invokes the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase
operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin.
A sector is Typically erased and verified in 1.0 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed, the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

FEATURES
*0.23 μm Process Technology
*Single 3.0 V Read, Program, and Erase
- Minimized system level power requirements
*Compatible with JEDEC-standard Commands
- Use the same software commands as E2PROMs
*Compatible with JEDEC-standard Worldwide Pinouts
- 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)
63-ball FBGA (Package suffix : PBT)
*Minimum 100,000 Program/Erase Cycles
*High Performance
- 80 ns maximum access time
*Sector Erase Architecture
- Eight 4 K word and sixty-three 32 K word sectors in word mode
- Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
- Any combination of sectors can be concurrently erased. Also supports full chip erase.
*Boot Code Sector Architecture
- T = Top sector
- B = Bottom sector
*HiddenROM Region
- 256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
- Factory serialized and protected to provide a secure electronic serial number (ESN)
*WP/ACC Input Pin
- At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
- At VACC, increases program performance
*Embedded EraseTM* Algorithms
- Automatically pre-programs and erases the chip or any sector
*Embedded ProgramTM* Algorithms
- Automatically writes and verifies data at specified address
*Data Polling and Toggle Bit feature for detection of program or erase cycle completion
*Ready/Busy output (RY/BY)
- Hardware method for detection of program or erase cycle completion
*Automatic sleep mode
- When addresses remain stable, automatically switch themselves to low power mode.
*Low VCC write inhibit ≤ 2.5 V
*Erase Suspend/Resume
- Suspends the erase operation to allow a read data and/or program in another sector within the same device
*Sector group protection
- Hardware method disables any combination of sector groups from program or erase operations
*Sector Group Protection Set function by Extended sector group protection command
*Fast Programming Function by Extended Command
*Temporary sector group unprotection
- Temporary sector group unprotection via the RESET pin.
*In accordance with CFI (Common Flash Memory Interface)
#*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MBM29LV320TE80TN, MBM29LV320TE90TN, MBM29LV320TE10TN, MBM29LV320TE80TR, MBM29LV320TE90TR, MBM29LV320TE10TR, MBM29LV320TE80PBT, MBM29LV320TE90PBT, MBM29LV320TE10PBT, MBM29LV320BE80TN, MBM29LV320BE90TN, MBM29LV320BE10TN, MBM29LV320BE80TR, MBM29LV320BE90TR, MBM29LV320BE10TR, MBM29LV320BE80PBT, MBM29LV320BE90PBT, MBM29LV320BE10PBT
 

MBM29LV320TE - FLASH MEMORY

General Description
 The S25FL016A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device.
The device consists of thirty-two sectors, each with 512 Kb memory.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output).
The devices are designed to be programmed in-system with the standard system 3.0 volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions.
Internally generated and regulated voltages are provided for the program operations.
This device does not require a VPP supply.

Distinctive Characteristics
* Single power supply operation
– Full voltage range: 2.7 to 3.6 V read and program operations
* Memory Architecture
– Thirty-two sectors with 512 Kb each
* Program
– Page Program (up to 256 bytes) in 1.4 ms (typical)
– Program operations are on a page by page basis
* Erase
– 0.5 s typical sector erase time
– 10 s typical bulk erase time
* Cycling Endurance
– 100,000 cycles per sector typical
* Data Retention
– 20 years typical
* Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward compatibility
* Process Technology
– Manufactured on 0.20 μm MirrorBit® process technology
* Package Option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-pin SO package (208 mils)
– 8-Contact WSON Package (6x8 mm), Pb Free Performance Characteristics
* Speed
– 50 MHz clock rate (maximum)
* Power Saving Standby Mode
– Standby Mode 50 μA (max)
– Deep Power Down Mode 1.3 μA (typical) Memory Protection Features
* Memory Protection
– W# pin works in conjunction with Status Register Bits to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only

 

S25FL016A - 16 Megabit CMOS 3.0 Volt Flash Memory with 50-MHz SPI (Serial Peripheral Interface) Bus

Architectural Advantages
* Single power supply operation
- 3 volt read, erase, and program operations
* Manufactured on 0.23 um MirrorBit process technology
* SecSi™ (Secured Silicon) Sector region
- 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence
- May be programmed and locked at the factory or by the customer
* Flexible sector architecture
- 256Mb: 512 32 Kword (64 Kbyte) sectors
- 128Mb: 256 32 Kword (64 Kbyte) sectors
- 64Mb (uniform sector models): 128 32 Kword (64 Kbyte) sectors or 128 32 Kword sectors
- 64Mb (boot sector models): 127 32 Kword (64 Kbyte) sectors + 8 4Kword (8Kbyte) boot sectors
- 32Mb (uniform sector models): 64 32Kword (64 Kbyte) sectors of 64 32Kword sectors
- 32Mb (boot sector models): 63 32Kword (64 Kbyte) sectors + 8 4Kword (8Kbyte) boot sectors
* Compatibility with JEDEC standards
- Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write protection
* 100,000 erase cycles typical per sector
* 20-year data retention typical

Performance Characteristics
* High performance
- 90 ns access time (128Mb, 64Mb, 32Mb), 100 ns access time (256Mb)
- 4-word/8-byte page read buffer
- 25 ns page read times (128Mb, 64Mb, 32Mb)
- 30 ns page read times (256Mb)
- 16-word/32-byte write buffer
- 16-word/32-byte write buffer reduces overall programming time for multiple-word updates
* Low power consumption (typical values at 3.0 V, 5 MHz)
- 18 mA typical active read current (64 Mb, 32 Mb)
- 25 mA typical active read current (256 Mb, 128 Mb)
- 50 mA typical erase/program current
- 1 μA typical standby mode current
* Package options
- 40-pin TSOP
- 48-pin TSOP
- 56-pin TSOP
- 64-ball Fortified BGA
- 48-ball fine-pitch BGA
- 63-ball fine-pitch BGA

Software & Hardware Features
* Software features
- Program Suspend & Resume: read other sectors before programming operation is completed
- Erase Suspend & Resume: read/program other sectors before an erase operation is completed
- Data# polling & toggle bits provide status
- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
- Unlock Bypass Program command reduces overall multiple-word programming time
* Hardware features
- Sector Group Protection: hardware-level method of preventing write operations within a sector group
- Temporary Sector Unprotect: VID-level method of charging code in locked sectors
- WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings on uniform sector models
- Hardware reset input (RESET#) resets device
- Ready/Busy# output (RY/BY#) detects program or erase cycle completion

S29GL256M
S29GL128M
S29GL064M
S29GL032M

 

S29GLXXXM - 256 Megabit, 128 Megabit, 64 Megabit, and 32Megabit, 3.0 Volt-only Page Mode Flash Memory featuring 0.23 um MirrorBit process technology

 FEATURES
• Single 5.0 V read, program and erase Minimizes system level power requirements
• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard byte-wide pinouts
- 32-pin PLCC (Package suffix: PD)
- 32-pin TSOP(I) (Package suffix: PF)
- 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
• Minimum 100,000 write/erase cycles
• High performance
- 55 ns maximum access time
• Sector erase architecture
- 8 equal size sectors of 64K bytes each
- Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Embedded Erase™ Algorithms
- Automatically pre-programs and erases the chip or any sector
• Embedded Program™ Algorithms
- Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Low VCC write inhibit £ 3.2 V
• Sector protection
- Hardware method disables any combination of sectors from write or erase operations
• Erase Suspend/Resume
- Suspends the erase operation to allow a read data in another sector within the same device

 GENERAL DESCRIPTION
The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.

 The standard MBM29F040C offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29F040C is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.

 The MBM29F040C is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

 Any individual sector is typically erased and verified in 1 second. (If already completely preprogrammed.) The device also features a sector erase architecture. The sector mode allows for 64K byte sectors of memory to be erased and reprogrammed without affecting other sectors. The MBM29F040C is erased when shipped from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7 or by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode.

 Fujitsu's Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability and cost effectiveness. The MBM29F040C memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

MBM29F040C-55
MBM29F040C-70
MBM29F040C-90  

MBM29F040C - FLASH MEMORY