DESCRIPTION
The UCD9240 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.
The UCD9240 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.
To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is
provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.
TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

FEATURES
*Fully Configurable Multi-Output and Multi-Phase Non-Isolated DC/DC PWM
Controller
*Controls Up To Four Voltage Rails and Up To Eight Phases
*Supports Switching Frequencies Up to 2MHz With 250 ps Duty-Cycle Resolution
*Up To 1mV Closed Loop Resolution
*Hardware-Accelerated, 3-Pole/3-Zero Compensator With Non-Linear Gain for
Improved Transient Performance
*Supports Multiple Soft-Start and Soft-Stop Configurations Including Prebias Start-up
*Supports Voltage Tracking, Margining and Sequencing
*Supports Current and Temperature Balancing for Multi-Phase Power Stages
*Supports Phase Adding/Shedding for Multi-Phase Power Stages
*Sync In /Out Pins Align DPWM Clocks Between Multiple UCD9240 Devices
*Fan Monitoring and Control
*12-Bit Digital Monitoring of Power Supply Parameters Including:
– Input Current and Voltage
– Output Current and Voltage
– Temperature at Each Power Stage
*Multiple Levels of Overcurrent Fault Protection:
– External Current Fault Inputs
– Analog Comparators Monitor Current Sense Voltage
– Current Continually Digitally Monitored
*Over and Undervoltage Fault Protection
*Overtemperature Fault Protection
*Enhanced Nonvolatile Memory With Error Correction Code (ECC)
*Device Operates From a Single Supply With an Internal Regulator Controller That Allows
Operation Over a Wide Supply Voltage Range
*Supported by Fusion Digital Power™ Designer, a Full Featured PC Based Design
Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS
*Industrial/ATE
*Networking Equipment
*Telecommunications Equipment
*Servers
*Storage Systems
*FPGA, DSP and Memory Power

UCD9240PFCR, UCD9240PFC  

UCD9240 - Digital PWM System Controller

Description
The OMAP-L137 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x™ DSP core. It provides significantly lower power than other members of the  MS320C6000™ platform of DSPs.
The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an synchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

Features
*Applications
- Industrial Control
- USB, Networking
- High-Speed Encoding
- Professional Audio
*Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
*Dual Core SoC
– 300-MHz ARM926EJ-S™ RISC MPU
– 300-MHz C674x™ VLIW DSP
*ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
*ARM9 Memory Architecture
*C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
*C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte L2 ROM
*Enhanced Direct-Memory-Access Controller 3 (EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
*TMS320C674x™ Floating Point VLIW DSP Core
– LSouapdp-oSrttore Architecture With Non-Aligned
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
– Two Multiply Functional Units
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and Program Redirecrion
*128K-Byte RAM Shared Memory
*Two External Memory Interfaces:
– EMIFA
– EMIFB
*Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
*LCD Controller
*Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
*Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
*Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
*USB 1.1 OHCI (Host) With Integrated PHY (USB1)
*USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
*Three Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capavle (McASP2)
- FIFO buffers for Transmit and Receive
*10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
*One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
*Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
*One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
*One 64-Bit General-Purpose Timer (Watch Dog)
*Three Enhanced Pulse Width Modulators (eHRPWM):
– Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
*Three 32-Bit Enhanced Capture Modules (eCAP):
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator(APWM)outputs
- Single Shot Capture of up to Four Event Time-Stamps
*Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)
*256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
*Commercial or Extended Temperature

OMAPL137ZKB3, XOMAPL137ZKB3  

OMAP-L137 - Low-Power Applications Processor

DESCRIPTION
The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference.
Different modes of operation enable or bypass various signal processing blocks.
The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.
The DAC5688 dual CMOS data bus provides 250MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing.
Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.
The DAC5688 allows both complex or real output.
An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair.
A digital Inverse SINC filter compensates for natural DAC Sin(X)/X frequency roll-off.
The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.
The DAC5688 is characterized for operation over the industrial temperature range of -40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

FEATURES
* Dual, 16-Bit, 800 MSPS DACs
* Dual, 16-Bit, 250 MSPS CMOS Input Data
- 16 Sample Input FIFO
- Flexible input data bus options
* High Performance
- 81 dBc ACLR WCDMA TM1 at 70 MHz
* 2x-32x Clock Multiplying PLL/VCO
* Selectable 2x–8x Interpolation Filters
- Stop-band Attenuation > 80 dB
* Complex Mixer with 32-Bit NCO
* Digital Quadrature Modulator Correction
- Gain, Phase and Offset Correction
* Digital Inverse SINC Filter
* 3- or 4-Wire Serial Control Interface
* On Chip 1.2-V Reference
* Differential Scalable Output: 2 to 20 mA
* Package: 64-pin 9´9mm QFN

APPLICATIONS
* Cellular Base Stations
* Broadband Wireless Access (BWA)
* WiMAX 802.16
* Fixed Wireless Backhaul
* Cable Modem Termination System (CMTS)  

DAC5688 - 16-BIT, 800 MSPS 2x–8x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER

DESCRIPTION
 The PGA112 and PGA113 (binary/scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in an MSOP-10 package.
The PGA116 and PGA117 (binary/scope fains) offer 10 analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware and software shutdown in a TSSOP-20 package.
All versions provide internal calibration channels for system-level calibration.
The channels are tied to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively.
VCAL, an external voltage connected to Channel 0, is used as the system calibration reference.
Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5,10, 20, 50, 100, and 200.

FEATURES
* Rail-to-Rail Input/Output
* Offset: 25mV (typ), 100mV (max)
* Zerø Drift: 0.35mV/°C (typ), 1.2mV/°C (max)
* Low Noise: 12nV/√Hz
* Input Offset Current: ±5nA max (+25°C)
* Gain Error: 0.1% max (G ≤ 32), 0.3% max (G > 32)
* Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
* Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
* Gain Switching Time: 200ns
* Two Channel MUX: PGA112, PGA113
  10 Channel MUX: PGA116, PGA117
* Four Internal Calibration Channels
* Amplifier Optimized for Driving CDAC ADCs
* Output Swing: 50mV to Supply Rails
* AVDD and DVDD for Mixed Voltage Systems
* IQ = 1.1mA (typ)
* Software/Hardware Shutdown: IQ ≤ 4mA (typ)
* Temperature Range: –40°C to +125°C
* SPI™ Interface (10MHz) with Daisy-Chain Capability

APPLICATIONS
* Remote e-Meter Reading
* Automatic Gain Control
* Portable Data Acquisition
* PC-Based Signal Acquisition Systems
* Test and Measurement
* Programmable Logic Controllers
* Battery-Powered Instruments
* Handheld Test Equipment

PGA113
PGA116
PGA117

 

PGA112 - Single-Supply, Single-Ended, Precision Programmable Gain Amplifier with MUX

description
The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TIE).
The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-mm triple-level-metal CMOS technology.
The TMS320C30’s internal busing and special DSP instruction set have the speed and flexibility to execute up to 50 MFLOPS (million floating-point operations per second).
The TMS320C30 optimizes speed by implementing functions in hardware that other processors implement through software or microcode.
This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle.
Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are enhanced greatly by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to dedicated coprocessor.

* High-Performance Floating-Point Digital
Signal Processor (DSP)
- TMS320C30-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
- TMS320C30-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
- TMS320C30-33 (5 V)
60-ns Instruction Cycle Time
183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS
- TMS320C30-27 (5 V)
74-ns Instruction Cycle Time
148.5 MOPS, 27 MFLOPS, 13.5 MIPS
* 32-Bit High-Performance CPU
* 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
* 32-Bit Instruction Word, 24-Bit Addresses
* Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
* One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block
* On-Chip Memory-Mapped Peripherals:
- Two Serial Ports
- Two 32-Bit Timers
- One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
* Two 32-Bit External Ports
* 24- and 13-Bit Addresses
* 0.7-mm Enhanced Performance Implanted CMOS (EPICE) Technology
* 208-Pin Plastic Quad Flat Package (PPM Suffix)
* 181-Pin Grid Array Ceramic Package (GEL Suffix)
* Eight Extended-Precision Registers
* Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
* Two- and Three-Operand Instructions
* Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle
* Block-Repeat Capability
* Zero-Overhead Loops With Single-Cycle Branches
* Conditional Calls and Returns
* Interlocked Instructions for Multiprocessing Support
* Two Sets of Memory Strobes (STRB and MSTRB) and One I/O Strobe (IOSTRB)
* Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation

TMS320C30GEL27

 

TMS320C30 - DIGITAL SIGNAL PROCESSOR