Description
Xilinx introduces the QPro™ XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM. The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that
require operation over the full military temperature range.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data
is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are
interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration
PROMs.

Features
*Operating Temperature Range: –55° C to +125°C
*Low-power advanced CMOS FLASH process memory cells immune to static single event upset
*In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
*IEEE Std 1149.1 boundary-scan (JTAG) support
*Cascadable for storing longer or multiple bitstreams
*Dual configuration modes
- Serial Slow/Fast configuration (up to 20 MHz)
- Parallel (up to 160 Mbps at 20 MHz)
*5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
*3.3V or 2.5V output capability
*Available in plastic VQ44 packaging only
*Design support using the Xilinx Alliance Series™ and Xilinx Foundation Series™ software packages
*JTAG command initiation of standard FPGA configuration

XQV300, XQV600, XQV1000  

XQ18V04 - Military 4Mbit ISP Configuration Flash PROM

Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.
A total of two function blocks provide 750 usable gates.
Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.

Features
*Lowest power 32 macrocell CPLD
*5.0 ns pin-to-pin logic delays
*System frequencies up to 200 MHz
*32 macrocells with 750 usable gates
*Available in small footprint packages
-48-ball CS BGA (36 user I/O pins)
-44-pin VQFP (36 user I/O)
-44-pin PLCC (36 user I/O)
*Optimized for 3.3V systems
-Ultra-low power operation
-5V tolerant I/O pins with 3.3V core supply
-Advanced 0.35 micron five layer metal EEPROM process
-Fast Zero Power™ (FZP) CMOS design technology
*Advanced system features
-In-system programming
-Input registers
-Predictable timing model
-Up to 23 available clocks per function block
-Excellent pin retention during design changes
-Full IEEE Standard 1149.1 boundary-scan (JTAG)
-Four global clocks
-Eight product term control terms per function block
*Fast ISP programming times
*Port Enable pin for dual function of JTAG ISP pins
*2.7V to 3.6V supply voltage at industrial temperature range
*Programmable slew rate control per macrocell
*Security bit prevents unauthorized access
*Refer to XPLA3 family data sheet (DS012) for architecture description

XCR3032XL-5VQ44C
XCR3032XL-10VQ44C  

XCR3032XL - 32 Macrocell CPLD

Description
The CoolRunner-II Automotive 128-macrocell device is designed for both high performance and low power applications.
This lends power savings to high-end communication equipment and high speed to battery operated devices.
Due to the low power stand-by and dynamic operation, overall system reliability is improved
This device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each Function Block.
The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch.
There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis.
Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt-trigger input is available on a per input pin basis.
In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis.
This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.
Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.

Features
* AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
* Guaranteed to meet full electrical specifications over TA = -40°C to +105°C with TJ Maximum = +125°C (Q-grade)
* Optimized for 1.8V systems
* Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
* Available in the following package options
- 100-pin VQFP with 80 user I/O
- 132-ball CP (0.5mm) BGA with 100 user I/O
- Pb-free only for all packages  

XA2C128 - CoolRunner-II Automotive CPLD

Description
 Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs.
Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin.
New data is available a short access time after each rising clock edge.
The FPGA generates the appropriate number of clock pulses to complete the configuration.
When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM.
When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.
After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins.
New data is available a short access time after each rising clock edge.
The data is clocked into the FPGA on the following rising edge of the CCLK.
A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device.
The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.

Features
* In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
- Endurance of 20,000 Program/Erase Cycles
- Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
* IEEE Std 1149.1 Boundary-Scan (JTAG) Support
* JTAG Command Initiation of Standard FPGA Configuration
* Simple Interface to the FPGA
* Cascadable for Storing Longer or Multiple Bitstreams
* Low-Power Advanced CMOS FLASH Process
* Dual Configuration Modes
- Serial Slow/Fast Configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
* 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
* 3.3V or 2.5V Output Capability
* Design Support Using the Xilinx ISE™ Foundation™ Software Packages
* Available in PC20, SO20, PC44, and VQ44 Packages
* Lead-Free (Pb-Free) Packaging

XC18V04
XC18V02
XC18V01
XC18V512

 

XC18V00 - In-System-Programmable Configuration PROMs

Description
 The CoolRunner™-II Automotive 32-macrocell device is designed for both high performance and low power applications.
This lends power savings to high-end communication equipment and high speed to battery operated devices.
Due to the low power stand-by and dynamic operation, overall system reliability is improved.
This device consists of two Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each Function Block.
The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch.
There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis.
Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.
A Schmitt trigger input is available on a per input pin basis.
In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
The CoolRunner-II Automotive 32-macrocell CPLD is I/O compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33.
This device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O banking.
Two I/O banks are available on the CoolRunner-II Automotive 32-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

Features
• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
• Guaranteed to meet full electrical specifications over TA = -40° C to +105° C with TJ Maximum = +125° C (Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
• Available in Pb-free 44-pin VQFP with 33 user I/O
• Advanced system features
- Fastest in system programming
 · 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
 · Optional DualEDGE triggered registers
- Global signal options with macrocell control
 · Multiple global clocks with phase selection per macrocell
 · Multiple global output enables
 · Global set/reset
- Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED drive
- Optional configurable grounds on unused I/Os
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
- PLA architecture
 · Superior pinout retention
 · 100% product term routability across function block
- Hot pluggable
Refer to the CoolRunner™-II Automotive CPLD family data sheet for architecture description.

XA2C32A-6VQG44I
XA2C32A-7VQG44Q  

XA2C32A - CoolRunner-II Automotive CPLD