Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair.
They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process.

Features
*Full duplex transmission over a single twisted pair
*Selectable 80 or 160 kbit/s line rate
*Adaptive echo cancellation
*Up to 3 km (9171) and 4 km (9172)
*ISDN compatible (2B+D) data format
*Transparent modem capability
*Frame synchronization and clock extraction
*Zarlink ST-BUS compatible
*Low power (typically 50 mW), single 5 V supply

Applications
*Digital subscriber lines
*High speed data transmission over twisted wires
*Digital PABX line cards and telephone sets
*80 or 160 kbit/s single chip modem

MT9171/72AE, MT9171/72AN, MT9171/72AP, MT9171/72APR, MT9171/72ANR
MT9171/72AE1, MT9171/72AP1, MT9171/72AN1, MT9171/72APR1, MT9171/72ANR1  

MT9171 - Digital Subscriber Interface Circuit Digital Network Interface Circuit

Description
The ZL38015 is a four channel Voice-Processor hardware platform designed to support advanced voice and digital signal processing applications available from Zarlink Semiconductor. The ZL38015 platform integrates Zarlink’s Voice Processor (ZVP) DSP Core with a number of internal peripherals including: 2 PCM ports, a 2048 tap Filter Co-processor, 2 Auxiliary Timers and a Watchdog Timer, 9 GPIO pins, UART, Slave SPI and Master SPI ports and a master/slave timing block.
The firmware products and manuals available at the release of this data sheet is the ZLS38233: 4 Channel Voice Echo Cancellor (VEC) with integrated DTMF Transceiver (Tx/Rx). If these applications do not meet your requirements, please contact your local Zarlink Sales Office for the latest firmware releases.

Features
*100 MHz (200 MIPs) Zarlink voice processor with Butterfly hardware accelerator and breakpoint/interrupt controller
*On-board Data (26 Kbytes), Instruction (24 Kbytes RAM and Boot (3 Kbytes) ROM
*2048 tap Filter co-processor shared across up to 16 separate functions in 128 tap increments
*Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec
*Separate slave (microcontroller) and master (Flash) SPI ports, maximum clock rate = 25 MHz
*Watchdog and 2 auxiliary timers
*11 General Purpose Input/Output (GPIO) pins
*General purpose UART port
*Bootloadable for future Zarlink software upgrades
*External oscillator or crystal/ceramic resonator
*1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
*IEEE-1149.1 compatible JTAG port

Applications
*Wireless Local Loop base stations and controllers
*Voice telephony gateways
*Digital, VoIP based and wireless PBX systems
*Echo Canceller pools
*Customer Premise equipment
*Integrated access devices
*SOHO gateways

ZL38015QCG1  

ZL38015 - Voice Processor

Description
The low thermal droop of this device allows baseband video transmission with minimum distortion.
The double-lens optical system provides for optimum coupling of power into the fiber.
It matches with the MF446 PIN Photodiode.

Features
* 780nm Surface-Emitting LED
* 55MHz Bandwidth
* Designed for 62.5/125μm fiber
* Low thermal droop

Applications
* Baseband Video
* Sensors
* General Purpose

MF359 ST
MF359 SMA

 

MF359 - 780nm - 55MHz High Performance LED

Description
This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office.
It provides simultaneous connections for up to 256 64 kbit/s channels.
Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream.
In addition, the MT89L80 provides microprocessor read and write access to individual ST-BUS channels.

Features
* 3.3 volt supply
* 5 V tolerant inputs and TTL compatible outputs.
* 256 x 256 channel non-blocking switch
* Accepts serial streams at 2.048 Mb/s
* Per-channel three-state control
* Patented per channel message mode
* Non-multiplexed microprocessor interface
* Zarlink ST-BUS compatible
* Low power consumption: typical 15 mW
* Pin compatible with the MT8980DP

Applications
* Key telephone systems
* PBX systems
* Small and medium voice switching systems

 

MT89L80 - CMOS ST-BUSTM Family Digital Switch

Description
 The MT90502 Multi-Channel AAL2 SAR bridges a standard TDM (Time Division Multiplexed) backplane to a standard ATM (Asynchronous Transfer Mode) bus.
The device provides the CPS (Common Part Sublayer) and SAR (Segmentation and Reassembly) engines.
The MT90502 has the capability of simultaneously processing 1023 bi-directional CIDs (AAL2 Channel Identifiers) and 1023 bi-directional VCs (Virtual Circuits).
The device can be connected directly to an H.110 compatible bus.
The TDM bus consists of 32 bi-directional serial data streams operating at 2.048, 4.096, or 8.192 Mbits/s.
The MT90502 directly accepts G.711 PCM (Pulse Code Modulation) and G.726 ADPCM (Adaptive Differential Pulse Code Modulation) traffic for packetisation.
For these two data formats, the device also implements silence suppression and comfort noise generation.
To support other voice compression algorithms, the MT90502 connects directly to commercially available DSPs through synchronous serial data streams.
The Variable Bit Rate (VBR) traffic is HDLC encapsulated and carried over the serial data streams.
The interface to the ATM domain is provided by three UTOPIA Level 1 ports (Ports A, B, and C). All three of the UTOPIA ports can operate in ATM (master) or PHY (slave) mode. Ports A and B combined, architects a compliant UTOPIA Level 2 Multi-PHY port.
The MT90502 provides the capability of routing ATM cells to different UTOPIA interfaces, SAR engine or CPU.
This feature can be used to connect another MT90502 (to support up to 2046 CID channels or 2046 phone calls) and/or to connect an external AAL1 and/or AAL5 SAR.

Features
* AAL2 Segmentation Reassembly device capable of simultaneously processing up to 1023 active CIDs (AAL2 Channel Identifier) and 1023 active VCs (Virtual Circuits).
* Support for up to 255 CIDs per VC. Maximum of 1023 CIDs.
* Implements AAL2 Common Part Sub-layer (CPS) functions specified in ITU I.363.2.
* Implements AAL2 Service Specific Convergence Sub-layer (SSCS) functions for G.711 PCM and G.726 ADPCM voice.
* Supports 44-byte PCM or ADPCM packet profiles specified in AF-VMOA-0145.00.
* CPS packet payload can support up to 64-bytes.
* Supports over-subscription of 10:1.
* H.100/H.110 compatible TDM bus for PCM or ADPCM data. Supports both master and slave TDM bus clock operation.
* TDM bus also supports compressed voice such as ITU G.723, G.728 and G.729 through HDLC encapsulation.
* Three UTOPIA Level 1 ports configurable as PHY or ATM allowing for connection to an external AAL5 SAR processor, or for chaining multiple MT90502 devices. Ports A & B are configurable as a single 8-bit UTOPIA Level 2 PHY port with 5 ADDR lines.
* UTOPIA module provides a cell switching function with a header translation.
* Performs silence suppression for PCM and ADPCM.
* Comfort noise generation.
* Capability to inject and recover CPS packets through the CPU host processor bus.
* 8-bit or 16-bit microprocessor port, configurable to Motorola or Intel timing.
* Single rail 3.3 V, 456 PBGA.
* IEEE 1149 (JTAG) interface.

Applications
* Gateway
* ATM Edge Switch
* Next Generation Digital Loop Carrier
* Multiservice Switching Platform
* 3rd Generation Mobile System Equipment

MT90502AG

 

MT90502 - Multi-Channel AAL2 SAR