The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs.

*2.5V or 3.3V operation
*200-MHz clock support
*LVPECL or LVCMOS/LVTTL clock input
*LVCMOS/LVTTL compatible outputs
*15 clock outputs: drive up to 30 clock lines
*1X and 1/2X configurable outputs
*Output three-state control
*350 ps maximum output-to-output skew
*Pin compatible with MPC949, MPC9449
*Available in Commercial and Industrial temperature range
*52-pin TQFP package

CY29949AXI, CY29949AXIT, CY29949AXC, CY29949AXCT

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