This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks.

*Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
*1:10 differential outputs
*External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input
*SSCG: Spread Aware™ for EMI reduction
*48-pin SSOP and TSSOP packages
*Conforms to JEDEC JC40 and JC42.5 DDR specifications


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