Specifications
*Density: 512M bits
*Organization
- 16M words × 8 bits × 4 banks (EDD5108AGTA)
- 8M words × 16 bits × 4 banks (EDD5116AGTA)
*Package: 66-pin plastic TSOP (II)
- Lead-free (RoHS compliant)
*Power supply: VDD, VDDQ = 2.5V ± 0.2V
*Data rate: 400Mbps/333Mbps/266Mbps (max.)
*Four internal banks for concurrent operation
*Interface: SSTL_2
*Burst lengths (BL): 2, 4, 8
*Burst type (BT):
- Sequential (2, 4, 8)
- Interleave (2, 4, 8)
*/CAS Latency (CL): 2, 2.5, 3
*Precharge: auto precharge option for each burst access
*Driver strength: normal/weak
*Refresh: auto-refresh, self-refresh
*Refresh cycles: 8192 cycles/64ms
- Average refresh period: 7.8μs
*Operating ambient temperature range
- TA = 0°C to +70°C

Features
*Double-data-rate architecture; two data transfers per clock cycle
*The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture
*Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver
*Data inputs, outputs, and DM are synchronized with DQS
*DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
*Data mask (DM) for write data

DDR400B, DDR400C, DDR333B, DDR266A, DDR266B
TAG ,

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