The K4S561632C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

*JEDEC standard 3.3V power supply
*LVTTL compatible with multiplexed address
*Four banks operation
*MRS cycle with address key programs
 -CAS latency (2 & 3)
 -Burst length (1, 2, 4, 8 & Full page)
 -Burst type (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock.
*Burst read single-bit write operation
*DQM for masking
*Auto & self refresh
*64ms refresh period (8K Cycle)

K4S561632C-TC/L60, K4S561632C-TC/L7C, K4S561632C-TC/L75

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