The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW.
The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip.

*Operating rate
*1250 MHz (Gigabit Ethernet) line rates
*Half and full VCO output rates
*Functionally compliant IEEE 802.3z Gigabit Ethernet standard
*Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference
*Receiver PLL provides clock and data recovery
*10-bit parallel TTL compatible interface
*Low-jitter serial LVPECL compatible interface
*Local loopback
*Single +3.3 V supply, 620 mW power dissipation
*64 PQFP or TQFP package
*Continuous downstream clocking from receiver
*Drives 30 m of Twinax cable directly

*Frame buffer
*Switched networks
*Data broadcast environments
*Proprietary extended backplanes

S2060A, S2060B, S2060C, S2060D

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