General Description
This device contains six independent gates each of which performs a buffer function.
The open-collector outputs require external pull-up resistors for proper logical operation.

DM7407M
DM7407N  

DM7407-Hex Buffers with High Voltage Open-Collector Outputs

DESCRIPTION
The AZ10/100LVEL11 is a differential 1:2 fanout gate.
The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open input conditions.
If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*265ps Propagation Delay
*5ps Skew Between Outputs
*High Bandwidth Output Transitions
*Internal Input Pulldown Resistors
*Operating Range of 3.0V to 5.5V
*Direct Replacement for ON Semi
-MC100LVEL11, MC10EL11
-& MC100EL11
*Transistor Count = 51

AZ100LVEL11

 

AZ10LVEL11 - ECL/PECL 1:2 Differential Fanout Buffer

DESCRIPTION
The MC74VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHC244 is a noninverting 3–state buffer, and has two active–low output enables.
This device is designed to be used with 3–state memory address drivers, etc.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

Features
* High Speed: tPD = 3.9ns (Typ) at VCC = 5V
* Low Power Dissipation: ICC = 4mA (Max) at TA = 25°C
* High Noise Immunity: VNIH = VNIL = 28% VCC
* Power Down Protection Provided on Inputs
* Balanced Propagation Delays
* Designed for 2V to 5.5V Operating Range
* Low Noise: VOLP = 0.9V (Max)
* Pin and Function Compatible with Other Standard Logic Families
* Latchup Performance Exceeds 300mA
* ESD Performance: HBM > 2000V; Machine Model > 200V
* Chip Complexity: 136 FETs or 34 Equivalent Gates

MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM  

MC74VHC244 - Octal Bus Buffer

Description
PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCIExpress clock generator for Intel server chipsets.
The device distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is LOW.
The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA.
When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated.
When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

Features
* Phase jitter fi lter for PCIe application
* Eight Pairs of Differential Clocks
* Low skew < 50ps
* Low Cycle-to-cycle jitter < 50ps
* Output Enable for all outputs
* Outputs Tristate control via SMBus
* Power Management Control
* Programmable PLL Bandwidth
* PLL or Fanout operation
* 3.3V Operation
* Packaging (Pb-Free & Green):
- 48-Pin SSOP (V)
- 48-Pin TSSOP (A)

PI6C20800SVE
PI6C20800SAE  

PI6C20800S - PCI Express 1:8 HCSL Clock Buffer

Description
 The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package.
Output is disabled when the associated output enable (OE) input is low.
To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current souring capability of the driver.
Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.

Features
* The basic gate function is lined up as hitachi uni logic series.
* Supplied on emboss taping for high speed automatic mounting.
* TTL compatible input level.
- Supply voltage range : 4.5 to 5.5 V
- Operating temperature range : –40 to +85°C
* All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
- All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
* Output current ±12 mA (@VCC = 4.5 V to 5.5 V)
* All the logical input has hysteresis voltage for the slow transition.

 

HD74LV1GT126A - Bus Buffer Gate with 3–state Output