Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks.

Features
*Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
*1:10 differential outputs
*External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input
*SSCG: Spread Aware™ for EMI reduction
*48-pin SSOP and TSSOP packages
*Conforms to JEDEC JC40 and JC42.5 DDR specifications

CY2SSTV850OC, CY2SSTV850OCT, CY2SSTV850ZC, CY2SSTV850ZCT  

CY2SSTV850 - Differential Clock Buffer/Driver

GENERAL DESCRIPTION
The ICS87993I is a PLL clock driver designed specifically for redundant clock tree designs.
The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signal frequency and phase while the other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay buffer performance.
The ICS87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input CLK signals.
Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H).
If that CLK is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated.

FEATURES
* 5 differential 3.3V LVPECL outputs
* Selectable differential clock inputs
* CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
* VCO range: 200MHz to 500MHz
* External feedback for “zero delay” clock regeneration with configurable frequencies
* Cycle-to-cycle jitter (RMS): 20ps (maximum)
* Output skew: 70ps (maximum), within one bank
* 3.3V supply voltage
* -40°C to 85°C ambient operating temperature
* Pin compatible with MPC993

ICS87993AYI
ICS87993AYIT  

ICS87993I - 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Description
PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCIExpress clock generator for Intel server chipsets.
The device distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is LOW.
The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA.
When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated.
When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

Features
* Phase jitter fi lter for PCIe application
* Eight Pairs of Differential Clocks
* Low skew < 50ps
* Low Cycle-to-cycle jitter < 50ps
* Output Enable for all outputs
* Outputs Tristate control via SMBus
* Power Management Control
* Programmable PLL Bandwidth
* PLL or Fanout operation
* 3.3V Operation
* Packaging (Pb-Free & Green):
- 48-Pin SSOP (V)
- 48-Pin TSSOP (A)

PI6C20800SVE
PI6C20800SAE  

PI6C20800S - PCI Express 1:8 HCSL Clock Buffer

General Description
The ICS932S422C is a main clock synthesizer for CK410-generation Intel server platforms.
The ICS932S422C is driven with a 14.318MHz crystal. It generates 5 CPU output pairs up to 400MHz and PCI-Express clocks at 100 or 200 MHz.
The 48 MHz USB clock is an exact 48.000 MHz clock.

Features/Benefits
* Supports spread spectrum modulation, 0 to -0.5% down spread
* Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error
* CPU clocks independent of SRC/PCI clocks
* D2/D3 SMBus address
* Compliant with PCIe Gen II phase noise specifications

Output Features
* 5 - 0.7V current-mode differential CPU pairs
* 4 - 0.7V current-mode differential SRC pair
* 4 - PCI (33MHz)
* 3 - PCICLK_F, (33MHz) free-running
* 1 - 48MHz
* 2 - REF, 14.318MHz

 

ICS932S422C - PCIe Gen 2 main Clock for Intel-based Servers

Description
The FS7140 / FS7145 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of electronic systems.
Via the I2Cbus interface, the FS714x can be adapted to many clock generation requirements.
The length of the reference and feedback dividers, their fine granularity, and the flexibility of the post divider make the FS714x the most flexible stand-alone phase-locked loop (PLL) clock generator available.

Features
* Extremely flexible and low-jitter phase-locked loop (PLL) frequency synthesis
* No external loop filter components needed
* 150MHz CMOS or 340MHz PECL outputs
* Completely configurable via I2C™-bus
* Up to four FS7140 or FS7145 can be used on a single I2C-bus
* 3.3V operation
* Independent on-chip crystal oscillator and external reference input
* Very low "cumulative" jitter

Applications
* Precision frequency synthesis
* Low-frequency clock multiplication
* Video line-locked clock generation
* Laser beam printers (FS7145)

13715-802-XTP
13715-201-XTP
13715-102-XTP
13715-202-XTP
13715-805-XTP
13715-806-XTP

 

FS7140-01 - Programmable Phase-Locked Loop Clock Generator