DESCRIPTION
The SP7682 or SP7682A provides a complete LED backlight and flash solution that is designed to drive 4 low current LEDs for backlighting and a single channel high current output for a LED flash. The SP7682 and SP7682A have serial interfaces that can program the backlight LED current in steps of 0.5mA up to 31.5mA and flash LED current in steps of 10mA up to 500mA. The SP7682A uses two single line serial interfaces for programming the backlight current and flash current. The SP7682 uses an I2C serial interface which also allows programming active, standby and shutdown states, selecting flash timeout periods and switching individual LEDs for the backlight. The data is loaded into internal registers upon power up and stored while in shutdown. When the chip is enabled, the stored values set the LED currents. The SP7682/SP7682A automatically detects 1x, 1.5x or 2x operation for optimal efficiency.

FEATURES
*Output current up to 500mA for Flash LED
*Up to 94% efficiency in 1x mode
*Triple mode 1x, 1.5x and 2x charge pump
*Built-in current setting DAC
*SP7682 - I2C serial interface
*SP7682A – Single Line Programmable Serial Interface
*2.4MHz switching frequency
*Flash LED output current adjustable in 10mA steps to 500mA
*Backlight LED output current adjustable in 0.5mA steps to 31.5mA
*Power-saving shutdown mode of 1μA
*Time Out function to protect the LED in Flash mode (2s)
*Thermal shutdown protection
*Built-in over-voltage and over-current protection
*Automatic soft start limits in-rush current
*Lead Free, RoHS Compliant Packaging: Space saving 16-pin 3X3mm QFN package

SP7682A, SP7682ER1-L, SP7682ER1-L/TR, SP7682EB, SP7682AER1-L, SP7682AER1-L/TR, SP7682AEB  

SP7682 - Backlight and Flash Driver in QFN 3mm x 3mm

GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes.
The 8 bits of data appear on DQ0–DQ7.
The Am29F016D is offered in 48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD) form.
For more information, refer to publication number 21551.
This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply.
A 12.0 volt VPP is not required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.23 μm process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 μm process technology.
The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states.
To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commandsare written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence.
This initiates the Embedded Program algorithm-an internal algorithm that automatically
times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm-an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions.
The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

DISTINCTIVE CHARACTERISTICS
*5.0 V ± 10%, single power supply operation
 -Minimizes system level power requirements
*Manufactured o 0.23 μm process technology
 -Compatible with 0.5 μm Am29F016 and 0.32 μm Am29F016B devices
*High performance
 -Access times as fast as 70 ns
*Low power consumption
 -25 mA typical active read current
 -30 mA typical program/erase current
 -1 μA typical standby current (standard access time to active mode)
*Flexible sector architecture
-32 uniform sectors of 64 Kbytes each
-Any combinatio of sectors ca be erased
-Supports full chip erase
-Group sector protection:
A hardware method of locking sector groups to prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code changes i previously locked sectors
*Embedded Algorithms
-Embedded Erase algorithm automatically preprograms and erases the entire chip or any  combinatio of designated sectors
-Embedded Program algorithm automatically writes and verifies bytes at specified addresses
*Unlock Bypass Program Command
-Reduces overall programming time whe issuing multiple program command sequences
*Minimum 1,000,000 program/erase cycles per sector guaranteed
*20-year data retentio at 125°C
-Reliable operatio for the life of the system
*Package options
-48-pi and 40-pi TSOP
-44-pi SO
-Know Good Die (KGD) (see publicatio number 21551)
*Compatible with JEDEC standards
-Pinout and software compatible with single-power-supply Flash standard
-Superior inadvertent write protection
*Data# Polling and toggle bits
-Provides a software method of detecting program or erase cycle completion
*Ready/Busy# output (RY/BY#)
-Provides a hardware method for detecting program or erase cycle completion
*Erase Suspend/Erase Resume
-Suspends a sector erase operatio to read data from, or program data to, a non-erasing sector,
the resumes the erase operation
*Hardware reset pi(RESET#)
-Resets internal state machine to the read mode

Am29F016D-70FI
Am29F016D-70E4C
Am29F016D-70F4E  

AM29F016D-16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

PRODUCT DESCRIPTION
The SST89E564RD, SST89V564RD, SST89E554RC, and SST89V554RC are members of the FlashFlex51 family of 8- bit microcontroller products designed and manufactured with the state-of-the-art SuperFlash CMOS semiconductor process technology.
The devices use the 8051 instruction set and are pin-for-pin compatible with standard 8051 microcontroller devices.
The device comes with 72/40 KByte of on-chip flash EEPROM program memory using SST’s patented and proprietary CMOS SuperFlash EEPROM technology with the SST’s field- enhancing, tunneling injector, split-gate memory cells.
The SuperFlash memory is partitioned into 2 independent program memory blocks.
The primary Super- Flash Block 0 occupies 64/32 KByte of internal program memory space and the secondary SuperFlash Block 1 occupies 8 KByte of internal program memory space.
The 8-KByte secondary SuperFlash block can be mapped to the lowest location of the 64/32 KByte address space; it can also be hidden from the program counter and used as an independent EEPROM-like data memory.
The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted with a special adapter and firmware for SST’s device.
During the power-on reset, the device can be configured as a slave to an external host for source code storage or as a master to an external host for an in-application programming (IAP) operation.
The device is designed to be programmed in-system and in-application on the printed circuit board for maximum flexibility.
The device is pre-programmed with an example of the bootstrap loader in the memory, demonstrating the initial user program code loading or subsequent user code updating
via the IAP operation.
An example bootstrap loader is available for the user’s reference and convenience only.
SST does not guarantee the functionality or the usefulness of the sample bootstrap loader.
Chip-Erase operations will erase the pre-programmed sample code.
In addition to 72/40 KByte of SuperFlash EEPROM program memory on-chip, the device can address up to 64 KByte of external program memory.
In addition to 1024 x8 bits of on-chip RAM, up to 64 KByte of external RAM can be addressed.
SST’s highly reliable, patented SuperFlash technology and memory cell architecture have a number of important advantages for designing and manufacturing flash EEPROMs.
These advantages translate into significant cost and reliability benefits for our customers.

FEATURES
*8-bit 8051-Compatible Microcontroller (MCU) with Embedded SuperFlash Memory
-Fully Software Compatible
-Development Toolset Compatible
-Pin-For-Pin Package Compatible
*SST89E564RD/SST89E554RC Operation
-0 to 40 MHz at 5V
*SST89V564RD/SST89V554RC Operation
-0 to 33 MHz at 3V
*Total 1 KByte Internal RAM (256 Byte + 768 Byte)
*Dual Block SuperFlash EEPROM
-SST89E564RD/SST89V564RD: 64 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks)
-SST89E554RC/SST89V554RC: 32 KByte primary block + 8 KByte secondary block (128-Byte sector size for both blocks)
-Individual Block Security Lock with SoftLock
-Concurrent Operation during In-Application Programming (IAP)
-Memory Overlay for Interrupt Support during IAP
*Support External Address Range up to 64 KByte of Program and Data Memory
*Three High-Current Port 1 pins (16 mA each)
*Three 16-bit Timers/Counters
*Full-Duplex, Enhanced UART
-Framing error detection
-Automatic address recognition
*Eight Interrupt Sources at 4 Priority Levels
*Programmable Watchdog Timer (WDT)
*Programmable Counter Array (PCA)
*Four 8-bit I/O Ports (32 I/O Pins)
*Second DPTR register
*Low EMI Mode (Inhibit ALE)
*SPI Serial Interface
*Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
*TTL- and CMOS-Compatible Logic Levels
*Brown-out Detection
*Low Power Modes
-Power-down Mode with External Interrupt Wake-up
-Idle Mode
*PDIP-40, PLCC-44 and TQFP-44 Packages
*Temperature Ranges:
-Commercial (0°C to +70°C)
-Industrial (-40°C to +85°C)

SST89V564RD
SST89V564RD
 

SST89E564RD - FlashFlex51 MCU

GENERAL DESCRIPTION
The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
* 16 Mbit of Flash Memory
* Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
* Bulk Erase (16 Mbit) in 20s (typical)
* Sector Erase (512 Kbit) in 1s (typical)
* Page Program (up to 256 Bytes) in 1.5ms (typical)
* 2.7 to 3.6V Single Supply Voltage
* SPI Bus Compatible Serial Interface
* 85MHz Clock Rate (maximum)
* Fast Read Dual Operation Instruction (3Bh/BBh)
* Deep Power-down Mode 1μA (typical)
* Top or Bottom Boot Block Configuration Available
* Electronic Signature
- JEDEC Standard Two-Byte Signature (2015h, Bottom;or 2025, Top)
- RES Instruction, One-Byte, Signature (14h)
* Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint

A2505PM-F
A2540PM-F
A2580PM-F
A2516PM-F  

A25L16P - 16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

PRODUCT DESCRIPTION
The SST39WF800A device is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
The SST39WF800A writes (Program or Erase) with a 1.65-1.95V power supply.
This device conforms to JEDEC standard pin assignments for x16 memories.
Featuring high-performance Word-Program, the SST39WF800A device provides a typical Word-Program time of 28 μsec.
The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation.
To protect against inadvertent writes, it has on-chip hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of applications, this device is offered with a guaranteed typical endurance of 100,000 cycles.
Data retention is rated at greater than 100 years.
The SST39WF800A device is suited for applications that require convenient and economical updating of program, configuration, or data memory.
For all system applications, it significantly improves performance and reliability, while lowering power consumption.
It inherently uses less energy during Erase and Program than alternative flash technologies.
When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application.
Since for any given voltage range, the SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.
These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred.
Therefore the system software or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39WF800A is offered in a 48-ball TFBGA package and a 48-ball Micro- Package.

FEATURES
* Organized as 512K x16
* Single Voltage Read and Write Operations
- 1.65-1.95V
* Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
* Low Power Consumption (typical values at 5 MHz)
- Active Current: 5 mA (typical)
- Standby Current: 5 μA (typical)
* Sector-Erase Capability
- Uniform 2 KWord sectors
* Block-Erase Capability
- Uniform 32 KWord blocks
* Fast Read Access Time
- 90 ns
* Latched Address and Data
* Fast Erase and Word-Program
- Sector-Erase Time: 36 ms (typical)
- Block-Erase Time: 36 ms (typical)
- Chip-Erase Time: 140 ms (typical)
- Word-Program Time: 28 μs (typical)
* Automatic Write Timing
- Internal VPP Generation
* End-of-Write Detection
- Toggle Bit
- Data# Polling
* CMOS I/O Compatibility
* JEDEC Standard
- Flash EEPROM Pinouts and command sets
* Packages Available
- 48-ball TFBGA (6mm x 8mm)
- 48-ball WFBGA (4mm x 6mm) Micro-Package
- 48-ball WFBGA (5mm x 6mm) Micro-Package
- 48-ball XFLGA (5mm x 6mm) Micro-Package
* All non-Pb (lead-free) devices are RoHS compliant  

SST39WF800A - 8 Mbit (x16) Multi-Purpose Flash