Description
The AT29LV1024 is a 3-volt only in-system Flash programmable and erasable rea donly memory (PEROM). Its 1 megabit of memory is organized as 65,536 words by 16bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 50 mA. The device endurance issuch that any sector can typically be written to in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29LV1024 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading f rom an EPROM. Reprogramming the AT29LV1024 is performed on a sector basis; 128 words of data are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 words of data are internally latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7 or I/O15. Once the end of a program cycle has been detected, a new access for a read or program can begin.

Features
*Single Voltage, Range 3V to 3.6V Supply
*3-Volt Only Read and Write Operation
*Software Protected Programming
*Fast Read Access Time - 150 ns
*Low Power Dissipation
– 15 mA Active Current
– 50 μA CMOS Standby Current
*Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 512 Sectors (128 words/sector)
– Internal Address and Data Latches for 128 Words
*Fast Sector Program Cycle Time - 20 ms
*Internal Program Control and Timer
*DATA Polling for End of Program Detection
*Typical Endurance > 10,000 Cycles
*CMOS and TTL Compatible Inputs and Outputs
*Commercial and Industrial Temperature Ranges

AT29LV1024-15JC, AT29LV1024-15TC, AT29LV1024-15JI, AT29LV1024-15TI, AT29LV1024-20JC, AT29LV1024-20TC, AT29LV1024-20JI, AT29LV1024-20TI, AT29LV1024-25JC, AT29LV1024-25TC, AT29LV1024-25JI, AT29LV1024-25TI  

AT29LV1024 - 1-Megabit(64K x 16) 3-volt Only Flash Memory

GENERAL DESCRIPTION
The Am29F016D is a 16 Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes.
The 8 bits of data appear on DQ0–DQ7.
The Am29F016D is offered in 48-pin TSOP, 40-pin TSOP, and 44-pin SO packages.
The device is also available in Known Good Die (KGD) form.
For more information, refer to publication number 21551.
This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply.
A 12.0 volt VPP is not required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.23 μm process technology, and offers all the features and benefits of the Am29F016, which was manufactured using 0.5 μm process technology.
The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microprocessors to operate without wait states.
To eliminate bus contention, the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls.
The device requires only a single 5.0 volt power supply for both read and write functions.
Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commandsare written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence.
This initiates the Embedded Program algorithm-an internal algorithm that automatically
times the program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This initiates the Embedded Erase algorithm-an internal algorithm that automatically
preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors.
The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions.
The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data.
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

DISTINCTIVE CHARACTERISTICS
*5.0 V ± 10%, single power supply operation
 -Minimizes system level power requirements
*Manufactured o 0.23 μm process technology
 -Compatible with 0.5 μm Am29F016 and 0.32 μm Am29F016B devices
*High performance
 -Access times as fast as 70 ns
*Low power consumption
 -25 mA typical active read current
 -30 mA typical program/erase current
 -1 μA typical standby current (standard access time to active mode)
*Flexible sector architecture
-32 uniform sectors of 64 Kbytes each
-Any combinatio of sectors ca be erased
-Supports full chip erase
-Group sector protection:
A hardware method of locking sector groups to prevent any program or erase operations within
that sector group
Temporary Sector Group Unprotect allows code changes i previously locked sectors
*Embedded Algorithms
-Embedded Erase algorithm automatically preprograms and erases the entire chip or any  combinatio of designated sectors
-Embedded Program algorithm automatically writes and verifies bytes at specified addresses
*Unlock Bypass Program Command
-Reduces overall programming time whe issuing multiple program command sequences
*Minimum 1,000,000 program/erase cycles per sector guaranteed
*20-year data retentio at 125°C
-Reliable operatio for the life of the system
*Package options
-48-pi and 40-pi TSOP
-44-pi SO
-Know Good Die (KGD) (see publicatio number 21551)
*Compatible with JEDEC standards
-Pinout and software compatible with single-power-supply Flash standard
-Superior inadvertent write protection
*Data# Polling and toggle bits
-Provides a software method of detecting program or erase cycle completion
*Ready/Busy# output (RY/BY#)
-Provides a hardware method for detecting program or erase cycle completion
*Erase Suspend/Erase Resume
-Suspends a sector erase operatio to read data from, or program data to, a non-erasing sector,
the resumes the erase operation
*Hardware reset pi(RESET#)
-Resets internal state machine to the read mode

Am29F016D-70FI
Am29F016D-70E4C
Am29F016D-70F4E  

AM29F016D-16 Megabit (2 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DESCRIPTION
The CAT28F512 is a high speed 64K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates.
Electrical erasure of the full memory contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard EPROM and E2PROM devices.
Programming and Erase are performed through an operation and verify algorithm.
The instructions are input via the I/O bus, using a two write cycle scheme.
Address and Data are latched to free the I/O bus and address bus during the write operation.
The CAT28F512 is manufactured using Catalyst’s advanced CMOS floating gate technology.
It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years.
The device is available in JEDEC approved 32-pin plastic DIP, 32-pin PLCC or 32-pin TSOP packages.

FEATURES
*Fast Read Access Time: 90/120/150 ns
*Low Power CMOS Dissipation:
-Active: 30 mA max (CMOS/TTL levels)
-Standby: 1 mA max (TTL levels)
-Standby: 100 mA max (CMOS levels)
*High Speed Programming:
-10 ms per byte
-1 Sec Typ Chip Program
*12.0V ± 5% Programming and Erase Voltage
*Electronic Signature
*Commercial, Industrial and Automotive Temperature Ranges
*Stop Timer for Program/Erase
*On-Chip Address and Data Latches
*JEDEC Standard Pinouts:
-32-pi*DIP
-32-pi*PLCC
-32-pi*TSOP ( 8 x 20)
*100,000 Program/Erase Cycles
*10 Year Data Retention

CAT28F512NI-90T
CAT28F512PI-90T  

CAT28F512 - 512K-Bit CMOS Flash Memory

GENERAL DESCRIPTION
The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
* 16 Mbit of Flash Memory
* Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
* Bulk Erase (16 Mbit) in 20s (typical)
* Sector Erase (512 Kbit) in 1s (typical)
* Page Program (up to 256 Bytes) in 1.5ms (typical)
* 2.7 to 3.6V Single Supply Voltage
* SPI Bus Compatible Serial Interface
* 85MHz Clock Rate (maximum)
* Fast Read Dual Operation Instruction (3Bh/BBh)
* Deep Power-down Mode 1μA (typical)
* Top or Bottom Boot Block Configuration Available
* Electronic Signature
- JEDEC Standard Two-Byte Signature (2015h, Bottom;or 2025, Top)
- RES Instruction, One-Byte, Signature (14h)
* Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint

A2505PM-F
A2540PM-F
A2580PM-F
A2516PM-F  

A25L16P - 16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

General Description
 The 24C32/ 24C64 provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 4096/8192 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low power and low-voltage operation are essential.
The 24C32/ 24C64 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface.

Features
* Wide Voltage Operation
- VCC = 1.8V to 5.5V
* Operating Ambient Temperature: -40。C to +85。C
* Internally Organized:
- 24C32, 4096 X 8 (32K bits)
- 24C64, 8192 X 8 (64K bits)
* Two-wire Serial Interface
* Schmitt Trigger, Filtered Inputs for Noise Suppression
* Bidirectional Data Transfer Protocol
* 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility
* Write Protect Pin for Hardware Data Protection
* 32-byte Page (32K, 64K) Write Modes
* Partial Page Writes Allowed
* Self-timed Write Cycle (5 ms max)
* High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
* 8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
* Die Sales: Wafer Form, Waffle Pack

24C64

 

24C32 - programmable read-only memory