Description
The ZL38015 is a four channel Voice-Processor hardware platform designed to support advanced voice and digital signal processing applications available from Zarlink Semiconductor. The ZL38015 platform integrates Zarlink’s Voice Processor (ZVP) DSP Core with a number of internal peripherals including: 2 PCM ports, a 2048 tap Filter Co-processor, 2 Auxiliary Timers and a Watchdog Timer, 9 GPIO pins, UART, Slave SPI and Master SPI ports and a master/slave timing block.
The firmware products and manuals available at the release of this data sheet is the ZLS38233: 4 Channel Voice Echo Cancellor (VEC) with integrated DTMF Transceiver (Tx/Rx). If these applications do not meet your requirements, please contact your local Zarlink Sales Office for the latest firmware releases.

Features
*100 MHz (200 MIPs) Zarlink voice processor with Butterfly hardware accelerator and breakpoint/interrupt controller
*On-board Data (26 Kbytes), Instruction (24 Kbytes RAM and Boot (3 Kbytes) ROM
*2048 tap Filter co-processor shared across up to 16 separate functions in 128 tap increments
*Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec
*Separate slave (microcontroller) and master (Flash) SPI ports, maximum clock rate = 25 MHz
*Watchdog and 2 auxiliary timers
*11 General Purpose Input/Output (GPIO) pins
*General purpose UART port
*Bootloadable for future Zarlink software upgrades
*External oscillator or crystal/ceramic resonator
*1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
*IEEE-1149.1 compatible JTAG port

Applications
*Wireless Local Loop base stations and controllers
*Voice telephony gateways
*Digital, VoIP based and wireless PBX systems
*Echo Canceller pools
*Customer Premise equipment
*Integrated access devices
*SOHO gateways

ZL38015QCG1  

ZL38015 - Voice Processor

Description
The OMAP-L137 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x™ DSP core. It provides significantly lower power than other members of the  MS320C6000™ platform of DSPs.
The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an synchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

Features
*Applications
- Industrial Control
- USB, Networking
- High-Speed Encoding
- Professional Audio
*Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
*Dual Core SoC
– 300-MHz ARM926EJ-S™ RISC MPU
– 300-MHz C674x™ VLIW DSP
*ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
*ARM9 Memory Architecture
*C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
*C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte L2 ROM
*Enhanced Direct-Memory-Access Controller 3 (EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
*TMS320C674x™ Floating Point VLIW DSP Core
– LSouapdp-oSrttore Architecture With Non-Aligned
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
– Two Multiply Functional Units
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and Program Redirecrion
*128K-Byte RAM Shared Memory
*Two External Memory Interfaces:
– EMIFA
– EMIFB
*Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
*LCD Controller
*Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
*Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
*Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
*USB 1.1 OHCI (Host) With Integrated PHY (USB1)
*USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
*Three Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capavle (McASP2)
- FIFO buffers for Transmit and Receive
*10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
*One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
*Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
*One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
*One 64-Bit General-Purpose Timer (Watch Dog)
*Three Enhanced Pulse Width Modulators (eHRPWM):
– Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
*Three 32-Bit Enhanced Capture Modules (eCAP):
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator(APWM)outputs
- Single Shot Capture of up to Four Event Time-Stamps
*Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)
*256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
*Commercial or Extended Temperature

OMAPL137ZKB3, XOMAPL137ZKB3  

OMAP-L137 - Low-Power Applications Processor

Description
Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements.
This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-12E, 0.25 μm (0.18 μm Leff)
Package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (E-PBGA)
Power (typical): TBDW at 133MHz, 1.5W at 200MHz, 2W at 266MHz

Features
* PowerPC® 405 32-bit RISC processor core operating up to 266MHz
* Synchronous DRAM (SDRAM) interface operating up to 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
* 4KB on-chip memory (OCM)
* External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and external peripherals
- Up to eight devices
- External Mastering supported
* DMA support for external peripherals, internal UART and memory
- Scatter-gather chaining supported
- Four channels
* PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
- Synchronous or asynchronous PCI Bus interface
- Internal or external PCI Bus Arbiter
* Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII)
* Programmable interrupt controller supports seven external and 19 internal edge triggered or levelsensitive interrupts
* Programmable timers
* Two serial ports (16550 compatible UART)
* One IIC interface
* General purpose I/O (GPIO) available
* Supports JTAG for board level testing
* Internal processor local Bus (PLB) runs at SDRAM interface frequency
* Supports PowerPC processor boot from PCI memory  

405GP - Power PC 405GP Embedded Processor

Overview
 The AL3000 provides all the necessary functions to implement IP Routing and Network Management for the RoX-II bus based Fast Ethernet and Gigabit Ethernet Switching System. The AL3000 is designed to interface to the Motorola PowerPC 800 Series, although the AL3000 could easily interface with any 32-bit microprocessor (non-PCI bus) with glue logic.
The AL3000 integrates high performance IPv4 Routing/Switching and Network Management engines.
These engines perform the following major functions:
* Routing Engine
- Four Quality of Service (QoS) Queues that support programmable weighted round-robin or strict priority to feed high-speed L3/L4 search engines
- IPv4 parser that classifies the frames and processes IP exception handling
- Routing Table Search function that performs L3/L4 search supporting 131,000 route entries, performs route table aging and maintains usage counters
- IP Field Replacement function that performs L2/L3/L4 field replacements and re-calculates L3/L4 checksums
- IP Route Trace function that provides frame header information to the CPU
* Network Management Engine
- Provides MAC services for the CPU to transmit and receive Ethernet frames to and from the RoX-II bus via high-speed DMA channels
- Gathers the MAC address updates in real-time for Bridge MIB support
- In conjunction with RoX-II bus Ethernet switch devices, provides Spanning- Tree support
- Provides access to all the internal registers of the RoX-II bus switch devices and their associated PHY devices
- Provides Ethernet related (EtherType), PHY related, and RMON MIB network\ statistics counters (48 counters per port)
The Routing Engine in the AL3000 pulls frames from RoX-II bus based switching devices, such as the AL126 or AL1022, according to the four priority queue control rules, and queues them to the search engine.
Network Management and other trapped frames (such as BPDU, GARP, etc.) are directly queued to the CPU DMA.
If a route entry is found, then all frame modification functions for IP routing are performed by the Field Replacement function.
Once fields are replaced, all L3/L4 checksums are updated, TTL decremented, and a new L2 FCS value is generated.
As a frame is routed, a frame header (first 64 bytes) can be sent to the CPU through a DMA channel for Router management or diagnostic applications.
Once a frame is routed, it is queued to one of the output ports of the RoX-II bus switching devices, and transmitted according to the new QoS priority classification.
Routed frames can also be sent to the CPU for forwarding to the WAN.
The AL3000 provides access to all registers and MAC address tables on RoX-II bus switching devices via remote register access commands.
The AL3000 also provides all the network statistic counters to support RMON groups 1 through 4 (EtherStats, History, History Control, Alarm) as well as Ethernet-like MIB.

Feature
- Provides routing functions to Allayer’s RoX-II bus Ethernet Switching devices
- Supports up to 32 Fast Ethernet or dual Gigabit ports on the RoX-II bus
- High performance Network (Layer 3) and Transport (Layer 4) address look-up engine
- Layer 2-, 3-, or 4-flow packet classification
- Programmable key search based on MAC and IP source and destination address, TCP socket, UDP socket or IP protocol number
- Supports up to 131,072 individual host route entries
- Supports 802.1q priority schemes and provides four Quality of Service (QoS) queues
- Provides Network Address Translation (NAT) per route database entry
- Provides support for IP Proxy Services with remappng of Layer 4 Socket replacements
- Programmable entry aging via internal timers and via external real-time clock
- Re-assigns VLAN tag and priority for each routed frame
- Programmable replacement of MAC and/or IP fields with associated Layer 3 and Layer 4 check-sum recalculation
- Supports 802.3ad port aggregation
- Supports virtually unlimited physical interfaces and as many logical interfaces as software is capable
- Congestion control for each physical interface and the overall routing engine
- Packet bandwidth control for each Layer 3 or Layer 4 flow
- Layer 3 buffer pool of up to 1024 frames
- Provides Ethernet, Bridge, and RMON MIB support for RoX II bus devices
- Six high-speed DMA engines
- 0.25 micron, 2.5V / 3.3V CMOS technology
- 456-pin BGA package

 

AL3000 - IP Frame Routing Processor

Description
 The IS-5114 is a highly integrated solution for dual-mode digital still-image and video cameras. It combines a number of functions that are required in such devices, including the following:
* The device is based on an ARM946ES microprocessor whose function is to control the entire
system, to capture and play back audio, and to multiplex compressed video and audio into a
single bit stream that can be delivered to the main CPU.
Most computationally-intensive functions are implemented in hardware which can be programmed according to user specifications, thus allowing the ARM® processor to be free for other user-defined functions such as advanced image and multimedia processing.
The processor has 8 KB + 8 KB of internal instruction/data cache which helps it to operate efficiently and use minimal DDR SDRAM bandwidth.
* The device supports imager sizes of up to 16 megapixels.
It accepts both Bayer RGB and CCIR-656 interfaces, which cover all possible CCD and CMOS sensors.
It supports progressive as well as interlaced (up to 4 fields) imagers, including the special readout modes of progressive VGA CCD imagers.
The device also supports a programmable delay on the external imager clock so that the highest quality images can be captured.
* The device has a high-performance still-image and video image processing block that
performs all the necessary functions to convert the image/video data to a format that can be
compressed in either JPEG or MPEG formats, as well as deliver image data to the LCD controller for a live view.
This block performs gain control, color recovery, Gamma correction, image enhancement, image correction, scaling, rotation, and conversion to the YC format.
All those functions have been implemented in the hardware to achieve the required performance
at very low power consumption figures.
In addition, there is a hardware block that collects statistics on the imager for auto-exposure (AE) and auto-white balancing (AWB) algorithms.
Those AE/AWB algorithms are performed in the embedded ARM9 CPU to allow customization of the application.
The current architecture also has the appropriate interfaces and sufficient performance to support a strobe-type flash light, as well as dark frame subtraction for low-level light conditions.
* The device has numerous display capabilities.
It has an integrated video encoder (double sampling) and two 10-bit video DACs running at up to 27 MHz to support direct display to high-definition TVs and projectors.
The device also has a 24-bit RGB output to interface to flat-panel TVs (LCDs and Plasma) at different VESA rates up to XGA (1024 x 768) resolution.
It supports both square pixel and CCIR-type formats and can display in NTSC or PAL mode
with the same crystal.
It also has an integrated LCD controller which can interface directly to various LCDs.
It directly supports a variety of LCD panels from Epson, Casio, AU, and Toppoly without the need for external ICs.
Finally, it has a digital video output interface which can supply composite, 8-bit YC (CCIR-656), 16-bit YC, RGB 565, or component (Y/Pr/Pb) formats.
* The device has a high-performance image scaler that can perform up and down scaling at
floating point resolutions.
* For video applications, a hardware video codec is included that supports MPEG-4 Simple
Profile (encode and decode) and Advanced Simple Profile (encode only) communication at
up to 30 fps VGA resolution.
The hardware video engine is a pipelined architecture which is also flexible enough to support JPEG compression/decompression, H.263, MPEG-2 encode(I/P frames) at 30 fps VGA, and MPEG-1 encode/decode at 24 fps VGA (I frames only).
The video codec can also be used to record and play back video clips including those taken from other digital cameras and mobile phones.
All performance figures are for half duplex operation.
Full duplex is possible, but the performance has not been characterized.
* The device utilizes a unified memory architecture using the DDR-SDRAM to capture, process, and play back images and video as well as to store program code and variables.
It supports SDRAM configurations of up to 1 gigabit.
* The device supports all Flash cards, including Multimedia Card (MMC), Secure Digital (SD),
Memory Stick Pro, SSFDC/SmartMedia/NAND Flash, and CompactFlash.
The Flash card interfaces can support read/write operations at the maximum speeds specified by the Flash cards.
* The device has an ATA/IDE controller with UDMA capability to stream video directly to hard
drives or CompactFlash devices.
* A static memory controller is included that supports up to eight 16 MB devices such as Flash,
SRAM, or other memory-mapped peripherals.
Both 8-bit and16-bit data buses are supported, with data accesses of up to 32 bits.
The number of wait states, and setup, hold, and data float times are programmable on a per device (chip select) basis.
* A general-purpose 10-bit 96 kHz DAC is available.
It can be used to control camera components such as the iris, shutter motor, lens motor, flash bulb, or AGC gain. It can also be used to drive audio output.
* A general-purpose 10-bit, 96 kHz ADC is available.
This ADC has four input channels, which can be used for such things as battery level checking, photo detection, focus sensing, or audio capture.
* The I2S- and AC’97-compatible audio data interface allows the device to connect with an
external stereo ADC/DAC to capture or play back voice or audio.
The device can encode captured audio in various popular formats, and can package it in the same bit stream as the video or inside compressed JPEG pictures.
It can also play back stand-alone audio such as MP3 files, or audio embedded in MPEG bit streams.
* The USB 2.0 high-speed slave controller can be used to connect to a PC for efficient downloading of captured images to the PC.
The USB 2.0 full-speed host controller allows the device to connect directly to printers and other slave devices.
* An IEEE 1394 link layer interface allows the device to stream video (compressed or uncompressed) to other devices.
* Two USART interfaces are included for serial communication.
They support standard baud rates of up to 460.8 kbps or non-standard rates of up to 4.875 Mbps in asynchronous mode.
They support rates of up to 19.5 Mbps in synchronous mode.
* The Serial Peripheral Interface (SPI) is used to boot from an external EEPROM.
Once the boot code is loaded inside the program memory, the CPU can download its code from any peripheral supported by the device, including non-volatile storage media.
With four chip select pins, the SPI can also be used to control other external devices at speeds of up to 24 Mbps.
* Three 16-bit and three 32-bit general-purpose timers are included which can be used to
generate interrupts to the internal CPU.
The 16-bit timers can also generate waveforms on their associated pins via pulse-width modulation (PWM) or other techniques.
They can also monitor and count external events on these pins.
* A dedicated watchdog timer is available which can provide an interrupt, an event on an external pin, or a reset to the internal CPU in the event that software is not responding as
expected.
Write access to the watchdog is protected by control access keys to prevent corruption of the watchdog should an error condition occur.
* A real-time clock is provided to keep track of the time.
It operates on its own power supplies, so the clock can keep running with very low power consumption even if the rest of the chip is unpowered.
Two pins are provided to control system power switching.
* The device provides a keyboard interface that can monitor up to 25 buttons.
* The device provides up to 8 external interrupt pins, depending on the system configuration,
which can be handled by the interrupt controller as either edge or level sensitive.
* Up to 130 pins can also be configured as GPIOs, depending on the system application.
* During normal operation, the power consumption may be minimized by disabling the clock of
any internal module that is not in use.
In order to further reduce power consumption, the main CPU clock can be divided to run at a slower speed.
In order to minimize power consumption when the device is not in use, a “sleep mode” is available that halts the operation of all logic and shuts down the oscillators and PLLs.
Recovery from the sleep mode occurs via the WKP (“wake-up”) pin, at which time the device begins execution from its previous state.

Features
* Advanced Processor for Dual-mode Digital Still Cameras and Video Recorders
* Supports Personal Video Recording Applications
* ARM946E-S™ Core with Enhanced DSP Capability for A/V Processing and System Control Functions, 8 KBytes Each for Instruction/Data Cache, Runs up to 96 MHz
* Supports Progressive and Interlaced CCD Imagers (up to 4 Fields)
* Image Processing Functions for CCD/CMOS Imagers
* Image Scaling and Rotation Hardware
* Video Encoder with Two DACs and Line Drivers for Composite or S-Video NTSC/PAL TV
* Digital Video Outputs Include: Composite, 16/8-bit YC (CCIR-656), RGB 565, 24-bit RGB, Component (Y/Pr/Pb), VESA up to XGA Resolutions
* Direct Interface to Casio, Epson, AU, and Toppoly LCDs
* Encodes/Decodes Images and Video: Baseline JPEG, MPEG-1 at 24 fps VGA, MPEG-4 at 30 fps VGA (Performance Figures are for Half Duplex)
* DDR SDRAM Interface Supports from 128 Mbits to 1 Gbit
* Unified Memory Architecture (Entire Program and Data Stored in DDR SDRAM)
* Support for All Flash Card Interfaces (MMC/SD, Memory Stick Pro™, SSFDC/SmartMedia, CompactFlash®)
* ATA/IDE Controller
* Static Memory Controller (Flash/SRAM) Supports up to Eight 16 MB Devices
* One DAC for Camera Control Functions and Audio Output
* Four ADC Channels for Monitoring Camera Analog Inputs (Audio, Switches, etc.)
* Audio Data Interface for Connection to External Stereo ADC/DAC
* USB 2.0 High-speed Slave and Full-speed Host Controllers for PC Camera and Printing Applications
* IEEE 1394 Link Layer Interface
* Two USART Interfaces and a Serial Peripheral Interface (SPI) for Loading Boot Code and Controlling Camera Components
* Six General-purpose Timers for Waveform Generation (PWM, etc.) and Event Monitoring
* Programmable Watchdog Timer and Real-time Clock
* Keyboard Interface Supports up to 25 Buttons
* Up to 8 External Interrupts and up to 130 Pins Configurable as General-purpose I/Os
* 280-ball BGA Package, 1.8V Core, and 1.8 to 3.3V I/O Operation

 

IS-5114 - High-Performance Digital/Video Camera Processor